A novel matching method for simultaneous multi-target recognition is proposed by jointly considering target's prior scattering knowledge and the polarization parameters of radar echoes. The matching coefficients a...A novel matching method for simultaneous multi-target recognition is proposed by jointly considering target's prior scattering knowledge and the polarization parameters of radar echoes. The matching coefficients are calculated for the judgment. MATLAB simulations show that several targets can be accurately recognized simultaneously, and a high recognition probability can be achieved in Monte Carlo simulations. The total execution time can be remarkably reduced in the Field Programmable Gate Array (FPGA) implementation of the matching procedure.展开更多
Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to i...Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to its compact size, thermal stability, and low power operation. The designs of trinary and quaternary signed-digit numbers based adders are presented using different polarized states of light. These proposed polarization-encoded based adders use much less switches and their speeds are higher than the intensity-encoded counterparts. Further, it will be shown that one of the proposed trinary signed-digit adders is twice as fast as a recently reported modified signed-digit adder.展开更多
The avalanche multiplication principle of electron multiplication CCD (EMCCD) was discussed on the basis of single type of carrier, and the multiplication model was built by using a classic piecewise ionization rate m...The avalanche multiplication principle of electron multiplication CCD (EMCCD) was discussed on the basis of single type of carrier, and the multiplication model was built by using a classic piecewise ionization rate model and avalanche multiplication integral formula. Wolff's ionization rate model was selected according to the structure and the multiplication gate amplitude of the actual devices. Compared the theoretical result with the multiplication curve of the actual device, it was found that only enough fringing field strength and multiplication area length could lead to adequate signal charge multiplication. The relationship between the multiplication gate amplitude and the total gain of the cascaded boosting EMCCD can be conveniently determined by using this model.展开更多
Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this ...Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.展开更多
1 Multiple-β transistor and linear AND-OR gate The high-speed and real-time processing of information requires a higher and higher operating speed for digital-integrated circuits. Making efforts to exploit silicon-in...1 Multiple-β transistor and linear AND-OR gate The high-speed and real-time processing of information requires a higher and higher operating speed for digital-integrated circuits. Making efforts to exploit silicon-integrated circuits with high speed, scientists pay attention to the bipolar-integrated circuits.展开更多
A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is exp...A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is experimentally realized using a thin epitaxial BCD process. Compared with the MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The high side offset voltage in the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure.展开更多
文摘A novel matching method for simultaneous multi-target recognition is proposed by jointly considering target's prior scattering knowledge and the polarization parameters of radar echoes. The matching coefficients are calculated for the judgment. MATLAB simulations show that several targets can be accurately recognized simultaneously, and a high recognition probability can be achieved in Monte Carlo simulations. The total execution time can be remarkably reduced in the Field Programmable Gate Array (FPGA) implementation of the matching procedure.
文摘Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to its compact size, thermal stability, and low power operation. The designs of trinary and quaternary signed-digit numbers based adders are presented using different polarized states of light. These proposed polarization-encoded based adders use much less switches and their speeds are higher than the intensity-encoded counterparts. Further, it will be shown that one of the proposed trinary signed-digit adders is twice as fast as a recently reported modified signed-digit adder.
文摘The avalanche multiplication principle of electron multiplication CCD (EMCCD) was discussed on the basis of single type of carrier, and the multiplication model was built by using a classic piecewise ionization rate model and avalanche multiplication integral formula. Wolff's ionization rate model was selected according to the structure and the multiplication gate amplitude of the actual devices. Compared the theoretical result with the multiplication curve of the actual device, it was found that only enough fringing field strength and multiplication area length could lead to adequate signal charge multiplication. The relationship between the multiplication gate amplitude and the total gain of the cascaded boosting EMCCD can be conveniently determined by using this model.
文摘Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.
文摘1 Multiple-β transistor and linear AND-OR gate The high-speed and real-time processing of information requires a higher and higher operating speed for digital-integrated circuits. Making efforts to exploit silicon-integrated circuits with high speed, scientists pay attention to the bipolar-integrated circuits.
基金This work was supported by the National Nature Science Foundation of China under Grant No.60436030.
文摘A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is experimentally realized using a thin epitaxial BCD process. Compared with the MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The high side offset voltage in the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure.
