FAULT DETECTION FOR MULTIPLE-VALUED LOGIC CIRCUITS WITH FANOUT-FREE

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.

SPECTRAL ANALYSIS OF SOME INDEPENDENCES OF MULTIPLE-VALUED LOGICAL FUNCTIONS ON THEIR VARIABLES

There are many kinds of special relationships between multiple-valued logical func-tions and their variables, and they are difficult to be judged from their expressions. In thispaper, some sufficient and necessary conditions of the independence and statistical independenceof multiple-valued logical functions on their variables are given. Some conditions of algebraicindependence of multiple-valued logical functions on some of their variables and the way to de-generate a function to the greatest extent are proposed, and some applications of these resultsare indicated. All the results are studied by using Chrestenson spectral techniques.

Design of AB^2 in Galois Fields Based on Multiple-Valued Logic

A new AB^2 operation in Galois Field GF(24)is presented and its systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure of the operation employs multiple-valued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the transistor and wire counts,and the initial delay.The performance is evaluated by HSPICE simulation with 0.18.μm CMOS technology.A comparison is conducted between our proposed implementation and those reported in the literature.The transistor counts,the wire counts and the initial delay in our MVL design show savings of about 23%,45%,and 72%,in comparison with the corresponding binary CMOS implementation.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementation.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2^k).

CIRCUIT TESTABLE DESIGN AND UNIVERSAL TEST SETS FOR MULTIPLE-VALUED LOGIC FUNCTIONS

The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.

A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock

A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterizedby improved storage capacity, flexible logic structure and reduced power dissipation.

Spectral characterization of the correlation-immunity of multiple-valued logic functions

Correlation-immunity is an important concept in cryptology. In ref. [1] Siegenthaler introduced the mathematical definition of correlation-immunity and used the correlation-immunity order of logic functions as a measure for cipher systems to defend against correlation attacks. In terms of Walsh transform, the correlation immunity of binary-valued logic functions, i.e. Boolean functions, was studied in ref. [2], and a

A Multiple-Valued Algebra for Modeling MOS VLSI Circuits at Switch-Level

A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper. Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a switch-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

A General Method in the Synthesis of Ternary Double Pass-Transistor Circuits

A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.

Design of quaternary logic circuits based on source-coupled logic

In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic source-coupled logic （SCL）. Its key components, the comparator and the output generator are both based on differential-pair circuit （DPC）, and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source- coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18 ~m CMOS technology. The power dissipa- tion, transistor numbers and delay are superior to corresponding binary CMOS implementation. Mul- tiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.

THE RESEARCH ON TERNARY TTL SCHMITT CIRCUITS

By analyzing the threshold-jumping of Schmitt circuits, this paper indicates that the core element realizing this function in binary TTL Schmitt circuits is the differential current switch with controllable threshold. Based on the characteristic having two kinds of signal-detection threshold in ternary TTL circuits, a ternary TTL Schmitt circuit having twice reactions of threshold-jumping is designed. The simulation with PSPICE proves that the designed circuit has ideal function of Schmitt circuits.

Systolic B-1 Circuit in Galois Fields Based on a Quaternary Logic Technique

In order to improve the circuit complexity and reduce the long latency of B-1 operations,a novel B-1 operation in Galois Field GF(24)is presented and the corresponding systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure employs multiplevalued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the initial delay and the transistor and wire counts.The performance is evaluated by HSPICE simulation in 0.18μm CMOS technology and a comparison is conducted between our proposed implementation and those reported in the literature.The initial delay and the sum of transistors and wires in our MVL design are about 43%and 13%lower,respectively,in comparison with other corresponding binary CMOS implementations.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementations.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2k).

Design of systolic B^N circuits in Galois fields based on quaternary logic

The BN operation is known as an efficient basic operation in Galois fields GF （2k）, and various algorithms and implementations using binary logic signals have already been proposed. In or- der to reduce the circuit complexity and long latency of BN operations, a novel algorithm and its sys- tolic architecture are proposed based on multiple-value logic （MVL）. In the very large scale integra- tion （VLSI） realization, a kind of multiple-valued current-mode （MVCM） circuit structure is presen- ted and in which the combination of dynamic source-coupled logic （SCL） and different-pair circuits （DPCs） is employed to improve the switching speed and reduce the power dissipation. The perform- ance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The transistor numbers and the delay are superior to corresponding binary CMOS implementation. The combination of MVCM cir- cuits and relevant algorithms based on MVL seems to be potential solution for high performance a- rithmetic operationsin Galois fields GF（2k）.

A NEW ASM DESIGN METHOD

A novel ASM one-zero-hot design method based upon ternary flip-flops with binaryconstruction as storage cells is presented.

RESEARCH INTO TERNARY EDGE-TRIGGERED JKL FLIP-FLOP

The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.

Designs of All-Optical Higher-Order Signed-Digit Adders Using Polarization-Encoded Based Terahertz-Optical-Asymmetric-Demultiplexer (TOAD)

Various designed circuits for multiple-valued all-optical arithmetic are demonstrated. The terahertz-optical-asymmetric-demultiplexer (TOAD) switch is used as the basic structure unit in the proposed circuits due to its compact size, thermal stability, and low power operation. The designs of trinary and quaternary signed-digit numbers based adders are presented using different polarized states of light. These proposed polarization-encoded based adders use much less switches and their speeds are higher than the intensity-encoded counterparts. Further, it will be shown that one of the proposed trinary signed-digit adders is twice as fast as a recently reported modified signed-digit adder.

Some Results on the Minimal Coverings of Precomplete Classes in Partial k-Valued Logic Functions

In completeness theories of multiple-valued logic, the characterization of Sheffer functions is an important issue. The solution can be reduced to determining the minimal coverings of precomplete classes. In this paper, someFull Symmetric Function Sets (m=3) are proved to be components of the minimal covering of precomplete classes inP k * . Keywords multiple-valued logic - completeness - Sheffer function - precomplete class NoteThis work is supported by the National Natural Science Foundation of China (Grant Nos.60083001 and 60375021).

Design of Multivalued Circuits Based on an Algebra for Current-Mode CMOS Multivalued Circuits

An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits are de-signed by algebraic means. The design method based on this algebra may offer a design simpler than the previously knowll ones.

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic （DTCTGAL） circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.