A high linearity current mode multiplier/divider with a wide dynamic range

A high linearity current mode multiplier/divider （CMM/D） with a wide dynamic range is presented. The proposed CMM/D is based on the voltage-current characteristic of the diode, thus wide dynamic range is achieved. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature and device parameters of the fabrication process. Furthermore, no extra bias current for all input signals is required and thus power saving is realized. With proper selection of establishing the input terminal, the proposed circuit can perform as a mulfifunction circuit to he operated as a multiplier/divider, without changing its topology. The proposed circuit is implemented in a 0.25μm BCD process and the chip area is 0.26 ~ 0.24 mm2. The simulation and measurement results show that the maximum static linearity error is 4-1.8% and the total harmonic distortion is 0.4% while the input current ranges from 0 to 200 μA.

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication.Therefore,high-speed and low-power multipliers design is mandatory for efficient computing systems.In designing low-energy dissipation circuits,reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity.This paper introduces an efficient signed/unsigned 4×4 reversible Vedic multiplier with minimum quantum cost.The Vedic multiplier is considered fast as it generates all partial product and their sum in one step.This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output.First,the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam(UT)Sutra.This multiplier consists of bitwise multiplication and adder compressors.Compared with Vedic multipliers in the literature,the proposed design has a quantum cost of 111 with a reduction of 94%compared to the previous design.It has a garbage output of 30 with optimization of the best-compared design.Second,the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers.Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters.DesignI has separate binary two’s complement(B2C)and MUX circuits,while DesignII combines binary two’s complement and MUX circuits in one circuit.DesignI shows the lowest quantum cost,231,regarding state-ofthe-art.DesignII has a quantum cost of 199,reducing to 86.14%of DesignI.The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design

Approximate computing is a popularfield for low power consumption that is used in several applications like image processing,video processing,multi-media and data mining.This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier.The multiplier is the most essen-tial element used for approximate computing where the power consumption is majorly based on its performance.There are several researchers are worked on the approximate multiplier for power reduction for a few decades,but the design of low power approximate multiplier is not so easy.This seems a bigger challenge for digital industries to design an approximate multiplier with low power and minimum error rate with higher accuracy.To overcome these issues,the digital circuits are applied to the Deep Learning(DL)approaches for higher accuracy.In recent times,DL is the method that is used for higher learning and prediction accuracy in severalfields.Therefore,the Long Short-Term Memory(LSTM)is a popular time series DL method is used in this work for approximate computing.To provide an optimal solution,the LSTM is combined with a meta-heuristics Jel-lyfish search optimisation technique to design an input aware deep learning-based approximate multiplier(DLAM).In this work,the jelly optimised LSTM model is used to enhance the error metrics performance of the Approximate multiplier.The optimal hyperparameters of the LSTM model are identified by jelly search opti-misation.Thisfine-tuning is used to obtain an optimal solution to perform an LSTM with higher accuracy.The proposed pre-trained LSTM model is used to generate approximate design libraries for the different truncation levels as a func-tion of area,delay,power and error metrics.The experimental results on an 8-bit multiplier with an image processing application shows that the proposed approx-imate computing multiplier achieved a superior area and power reduction with very good results on error rates.

FPGA Optimized Accelerator of DCNN with Fast Data Readout and Multiplier Sharing Strategy

With the continuous development of deep learning,Deep Convolutional Neural Network(DCNN)has attracted wide attention in the industry due to its high accuracy in image classification.Compared with other DCNN hard-ware deployment platforms,Field Programmable Gate Array(FPGA)has the advantages of being programmable,low power consumption,parallelism,and low cost.However,the enormous amount of calculation of DCNN and the limited logic capacity of FPGA restrict the energy efficiency of the DCNN accelerator.The traditional sequential sliding window method can improve the throughput of the DCNN accelerator by data multiplexing,but this method’s data multiplexing rate is low because it repeatedly reads the data between rows.This paper proposes a fast data readout strategy via the circular sliding window data reading method,it can improve the multiplexing rate of data between rows by optimizing the memory access order of input data.In addition,the multiplication bit width of the DCNN accelerator is much smaller than that of the Digital Signal Processing(DSP)on the FPGA,which means that there will be a waste of resources if a multiplication uses a single DSP.A multiplier sharing strategy is proposed,the multiplier of the accelerator is customized so that a single DSP block can complete multiple groups of 4,6,and 8-bit signed multiplication in parallel.Finally,based on two strategies of appeal,an FPGA optimized accelerator is proposed.The accelerator is customized by Verilog language and deployed on Xilinx VCU118.When the accelerator recognizes the CIRFAR-10 dataset,its energy efficiency is 39.98 GOPS/W,which provides 1.73×speedup energy efficiency over previous DCNN FPGA accelerators.When the accelerator recognizes the IMAGENET dataset,its energy efficiency is 41.12 GOPS/W,which shows 1.28×−3.14×energy efficiency compared with others.

Optimization of DC Resistance Divider Up to 1200 kV Using Thermal and Electric Field Analysis

Self-heating and electric field distribution are the primary factors affecting the accuracy of the Ultra High Voltage Direct Current(UHVDC)resistive divider.Reducing the internal temperature rise of the voltage divider caused by self-heating,reducing the maximum electric field strength of the voltage divider,and uniform electric field distribution can effectively improve the UHVDC resistive divider’s accuracy.In this paper,thermal analysis and electric field distribution optimization design of 1200 kV UHVDC resistive divider are carried out:(1)Using the proposed iterative algorithm,the heat dissipation and temperature distribution of the high voltage DC resistive divider are studied,and the influence of the ambient temperature and the power of the divider on the temperature of the insulating medium of the divider is analyzed;(2)Established the finite element models of 1200 kV and 2×600 kV DC resistive dividers,analyzed the influence of the size of the grading ring and the installation position on the maximum electric field strength of the voltage divider,and calculated the impact of the shielding resistor layer on the vicinity of the measuring resistor layer.The research indicates that:(1)The temperature of the insulating medium is linearly related to the horsepower of the voltage divider and the ambient temperature;(2)After the optimized design of the electric field,the maximum electric field strength of the 1200 kV DC resistive divider is reduced to 1471 V/mm,which is about 24% lower than that of the unoptimized design;(3)Installing the shielding resistor layer can significantly improve the electric field near the measuring resistor layer.This paper has an important reference function for improving the accuracy of the UHVDC resistive divider.

A Miniaturized Broadband Wilkinson Power Divider Using Micro-Strip Branch Lines

A miniaturized broadband Wilkinson power divider is proposed. Micro-strip branch lines are introduced to replace multiple resistors used in multi-stage Wilkinson power dividers to increase the bandwidth of single-stage Wilkinson power dividers. To demonstrate its performance, an improved single-stage Wilkinson power divider with four micro-strip branch lines was designed. Simulated results show that the insert loss is better than 3.2 dB, the input return loss, output return loss, and isolation are better than 15 dB respectively, across a 76% bandwidth from 18 to 40 GHz. .

Analysis of Mobile and Internet Network Coverage: Propagation of Electromagnetic Waves and Concept of Digital Divide in Burundi

Mobile and Internet network coverage plays an important role in digital transformation and the exploitation of new services. The evolution of mobile networks from the first generation (1G) to the 5th generation is still a long process. 2G networks have developed the messaging service, which complements the already operational voice service. 2G technology has rapidly progressed to the third generation (3G), incorporating multimedia data transmission techniques. It then progressed to fourth generation (4G) and LTE (Long Term Evolution), increasing the transmission speed to improve 3G. Currently, developed countries have already moved to 5G. In developing countries, including Burundi, a member of the East African Community (ECA) where more than 80% are connected to 2G technologies, 40% are connected to the 3G network and 25% to the 4G network and are not yet connected to the 5G network and then still a process. The objective of this article is to analyze the coverage of 2G, 3G and 4G networks in Burundi. This analysis will make it possible to identify possible deficits in order to reduce the digital divide between connected urban areas and remote rural areas. Furthermore, this analysis will draw the attention of decision-makers to the need to deploy networks and coverage to allow the population to access mobile and Internet services and thus enable the digitalization of the population. Finally, this article shows the level of coverage, the digital divide and an overview of the deployment of base stations (BTS) throughout the country to promote the transformation and digital inclusion of services.

A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider

A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

Integrated Low-Power CMOS VCO and Its Divide-by-2 Dividers

An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.

The Multiplier Algebra of a Ternary Algebra

In this article, we have given the definition of the relative double multiplier (quasi-multiplier) on a ternary algebra,and studied the isomorphic problem of the multiplier algebra M(A,e) of a ternary algerbra A.

Fast alternating direction method of multipliers for total-variation-based image restoration

A novel algorithm, i.e. the fast alternating direction method of multipliers （ADMM）, is applied to solve the classical total-variation （ TV ）-based model for image reconstruction. First, the TV-based model is reformulated as a linear equality constrained problem where the objective function is separable. Then, by introducing the augmented Lagrangian function, the two variables are alternatively minimized by the Gauss-Seidel idea. Finally, the dual variable is updated. Because the approach makes full use of the special structure of the problem and decomposes the original problem into several low-dimensional sub-problems, the per iteration computational complexity of the approach is dominated by two fast Fourier transforms. Elementary experimental results indicate that the proposed approach is more stable and efficient compared with some state-of-the-art algorithms.

OTA MACROMODEL AND QUARTER-SQUARE MULTIPLIER

This paper presents a new kind of macromodel of OTA,which can be used to solve the problem in which the two port macromodel couldnt reflect some functions of the OTA.The new model also opens up a new way for the simulation of the OTA circuit.This paper discusses the way of designing this model and simulating it in SPICE.The result proves its reasonable design and its simplicity in structure.In the application of this model,we design a complete symmetric double differential quarter square OTA multiplying unit by using four three port OTA macromodels.It successfully solved the problem of the unsymmetry of two input ports in an OTA multiplying unit.This result fully agrees with the experiment.

0.18μm CMOS programmable frequency divider design for DVB-T

The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.

Multipliers of Hardy Spaces

本文刻划了Hardy空间H^p（1≤p≤∞）到Bloch空间的乘子，推广了前人的结果。

π-quasitriangular group-cograded multiplier Hopf algebras

Let G be a group and （A, B） be a pair of multiplier Hopf algebras, where B is regular G-cograded. Let π be a crossing action of G on B, D^π=A^cop∝B=＋p∈GDπ^p with Dπ^p=A^cop∝Bp, is the Drinfeld double of the pair （A, B）, and then the deformation D^π becomes a multiplier Hopf algebra. B×A can be considered as a subalgebra of M（D^π×D^π）, the image of element b×a in B×A is （1∝b）×（a∝1） in M（D^π×D^π）. Let W =∑αWα∈ M（B×A） be a π-canonical multiplier for the pair （A, B） with Wα∈M（Bα×A） for all α∈G. The image of W in M（D^π×D^π）is a π-quasitriangular structure over D^π.

Multipliers on Weighted Hardy Spaces over Locally Compact Vilenkin Groups

This paper is devoted to study the atomic decomposition of the weighted Hardy space on Vilenkin groups and a weighted Hp multiplier theorem.

An 8.5GHz 1∶8 Frequency Divider in 0.35μm CMOS Technology

An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.

Images of triple gas electron multiplier with pixel-pads

Testing of a triple gas electron multiplier （GEM） with pixel-pads is described. Images by scanning and suspending radioactive sources were obtained by using 96 channels digital data acquisition （DAQ） system which was composed of 96 8×8 mm2 pads and associated electronics channels.

The Art of Power Dividing:A Review for State-of-the-Art Planar Power Dividers

In this paper,massive state-of-theart planar power dividers are presented and discussed. The innovations of these superiorly-performanced power dividers lie in the performance breakthrough,physical configurations and function integrations. Eventually,based on the trend presented,the future of the power dividers is predicted. This paper might have inspiration significance to illuminate the way for the development of power dividers.

ON SOME GENERALIZED DIFFERENCE PARANORMED SEQUENCE SPACES ASSOCIATED WITH MULTIPLIER SEQUENCE DEFINED BY MODULUS FUNCTION

In this article we introduce the paranormed sequence spaces （f,A, Am,p）, c0（f,A,Am,p） and L00（f,A, Am,p）, associated with the multiplier sequence ∧ = （hk）, defined by a modulus function f. We study their different properties like solidness, symmetricity, completeness etc. and prove some inclusion results.