The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si ...The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si O2/p-Si are also characterized. After N2-plasma treatment, the nitrogen atoms are incorporated into HfO2 film and may passivate the oxygen vacancy states. The surface roughness of HfO2 film can also be reduced. Those improvements of HfO2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N2-plasma is introduced into Au nanocrystal(NC) nonvolatile memory to treat the HfO2 blocking layer. For the N2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N2-plasma treated device. It can be concluded that the N2-plasma treatment method can be applied to future nonvolatile memory applications.展开更多
Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we...Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor(CMOS) technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size(12 nm) and areal density(1.8×10^(11)/cm^2) of Si-NCs.The program/erase(P/E) speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.展开更多
Based on the capacitive coupling formalism, an analytic model for calculating the drain currents of the quantum-dots floating-gate memory cell is proposed. Using this model, one can calculate numerically the drain cur...Based on the capacitive coupling formalism, an analytic model for calculating the drain currents of the quantum-dots floating-gate memory cell is proposed. Using this model, one can calculate numerically the drain currents of linear, saturation and subthreshold regions of the device with/without charges stored on the floating dots. The read operation process of an n-channel Si quantum-dots floating-gate nano-memory cell is discussed after calculating the drain currents versus the drain to source voltages and control gate voltages in both high and low threshold states respectively.展开更多
Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method, followed by thermal annealing to form the Si nanocrystals(Si-NCs) embedded in Si Nx floating gate MOS structures. The c...Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method, followed by thermal annealing to form the Si nanocrystals(Si-NCs) embedded in Si Nx floating gate MOS structures. The capacitance–voltage(C–V), current–voltage(I–V), and admittance–voltage(G–V) measurements are used to investigate the charging characteristics. It is found that the maximum flat band voltage shift(△VFB) due to full charged holes(~ 6.2 V) is much larger than that due to full charged electrons(~ 1 V). The charging displacement current peaks of electrons and holes can be also observed by the I–V measurements, respectively. From the G–V measurements we find that the hole injection is influenced by the oxide hole traps which are located near the Si O2/Si-substrate interface. Combining the results of C–V and G–V measurements, we find that the hole charging of the Si-NCs occurs via a two-step tunneling mechanism. The evolution of G–V peak originated from oxide traps exhibits the process of hole injection into these defects and transferring to the Si-NCs.展开更多
The rapid thermal annealing (RTA) nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature (usually 600 900 ℃) in the RTA process will worsen the per-...The rapid thermal annealing (RTA) nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature (usually 600 900 ℃) in the RTA process will worsen the per- formance and reliability of devices. A novel method has been proposed to grow metal nanocrystal by synchronous in situ nano-crystallization of metal thin film (SINC), which is able to resolve the problems mentioned above. Com- pared with Ni nanocrystals (NCs) formed by RTA, Ni NCs prepared by SINC can obtain more energy to crystallize, and its crystallization temperature is greatly reduced. A large memory window (2.78 V) was observed for Ni NCs deposited by SINC at 300 ℃. However, the largest window is only 1.26 V for Ni NCs formed by RTA at 600 ℃. A large change (from 0.20 to 4.59 V) of the memory window was observed while the operation voltage increased from 0 to 4-10 V, which is due to an occurrence of strong carrier trapping in Ni NCs. Flat-band voltage shift rapidly increases to its saturation value, which indicates that electron/hole trapping in Ni NCs mainly occurs at the initial stage of the program/erase process. A theoretical model was proposed to characterize the charging and discharging processes.展开更多
The stress induced martensitic phase transformation of spherical ZrCu nanocrystals embedded in an amorphous matrix was studied in this paper. Microstructural observations revealed that the martensitic transformation o...The stress induced martensitic phase transformation of spherical ZrCu nanocrystals embedded in an amorphous matrix was studied in this paper. Microstructural observations revealed that the martensitic transformation of the nanocrystal was hindered by the surrounding amorphous coating. The existence of two-step transformation from the austenite phase(B2) to the base structure martensite(B19') and finally to the most stable superstructure martensite(Cm) was also demonstrated. The Cm martensite with(021) type I twinning symmetrically accommodation was surrounded by the B19' martensite with dislocation morphologies.展开更多
基金supported by the High Level Talent Project of Xiamen University of Technology,China(Grant Nos.YKJ16012R and YKJ16016R)the National Natural Science Foundation of China(Grant No.51702271)
文摘The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si O2/p-Si are also characterized. After N2-plasma treatment, the nitrogen atoms are incorporated into HfO2 film and may passivate the oxygen vacancy states. The surface roughness of HfO2 film can also be reduced. Those improvements of HfO2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N2-plasma is introduced into Au nanocrystal(NC) nonvolatile memory to treat the HfO2 blocking layer. For the N2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N2-plasma treated device. It can be concluded that the N2-plasma treatment method can be applied to future nonvolatile memory applications.
基金Project supported by the State Key Development Program for Basic Research of China(Grant No.2010CB934402)the National Natural Science Foundation of China(Grant Nos.11374153,61571221,and 61071008)
文摘Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor(CMOS) technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size(12 nm) and areal density(1.8×10^(11)/cm^2) of Si-NCs.The program/erase(P/E) speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.
基金Foundation for Key Youth Teachers from Hunan Province(521105237)
文摘Based on the capacitive coupling formalism, an analytic model for calculating the drain currents of the quantum-dots floating-gate memory cell is proposed. Using this model, one can calculate numerically the drain currents of linear, saturation and subthreshold regions of the device with/without charges stored on the floating dots. The read operation process of an n-channel Si quantum-dots floating-gate nano-memory cell is discussed after calculating the drain currents versus the drain to source voltages and control gate voltages in both high and low threshold states respectively.
基金Project supported by the National Basic Research Program of China(Grant No.2010CB934402)the National Natural Science Foundation of China(Grant No.11374153)
文摘Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method, followed by thermal annealing to form the Si nanocrystals(Si-NCs) embedded in Si Nx floating gate MOS structures. The capacitance–voltage(C–V), current–voltage(I–V), and admittance–voltage(G–V) measurements are used to investigate the charging characteristics. It is found that the maximum flat band voltage shift(△VFB) due to full charged holes(~ 6.2 V) is much larger than that due to full charged electrons(~ 1 V). The charging displacement current peaks of electrons and holes can be also observed by the I–V measurements, respectively. From the G–V measurements we find that the hole injection is influenced by the oxide hole traps which are located near the Si O2/Si-substrate interface. Combining the results of C–V and G–V measurements, we find that the hole charging of the Si-NCs occurs via a two-step tunneling mechanism. The evolution of G–V peak originated from oxide traps exhibits the process of hole injection into these defects and transferring to the Si-NCs.
基金Project supported by the National Natural Science Foundation of China(No.61076055)the Open Project Program of Surface Physics Laboratory(National Key Laboratory)of Fudan University(No.KL2011_04)
文摘The rapid thermal annealing (RTA) nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature (usually 600 900 ℃) in the RTA process will worsen the per- formance and reliability of devices. A novel method has been proposed to grow metal nanocrystal by synchronous in situ nano-crystallization of metal thin film (SINC), which is able to resolve the problems mentioned above. Com- pared with Ni nanocrystals (NCs) formed by RTA, Ni NCs prepared by SINC can obtain more energy to crystallize, and its crystallization temperature is greatly reduced. A large memory window (2.78 V) was observed for Ni NCs deposited by SINC at 300 ℃. However, the largest window is only 1.26 V for Ni NCs formed by RTA at 600 ℃. A large change (from 0.20 to 4.59 V) of the memory window was observed while the operation voltage increased from 0 to 4-10 V, which is due to an occurrence of strong carrier trapping in Ni NCs. Flat-band voltage shift rapidly increases to its saturation value, which indicates that electron/hole trapping in Ni NCs mainly occurs at the initial stage of the program/erase process. A theoretical model was proposed to characterize the charging and discharging processes.
基金supported by the National Natural Science Foundation of China (Nos. 51171052 and 51322102)National Basic Research Program of China (973 Projects) (Nos. 2011CB012904 and 2012CB619400)+2 种基金Doctoral Program Foundation of Institutions of Higher Education of China (No. 20112302130006)the Fundamental Research Funds for the Central Universities (HIT. BRET Ⅲ 20120the1)the State Key Lab of Advanced Metals and Materials (2015-Z01)
文摘The stress induced martensitic phase transformation of spherical ZrCu nanocrystals embedded in an amorphous matrix was studied in this paper. Microstructural observations revealed that the martensitic transformation of the nanocrystal was hindered by the surrounding amorphous coating. The existence of two-step transformation from the austenite phase(B2) to the base structure martensite(B19') and finally to the most stable superstructure martensite(Cm) was also demonstrated. The Cm martensite with(021) type I twinning symmetrically accommodation was surrounded by the B19' martensite with dislocation morphologies.