Nanoimprint lithography(NIL) is an emerging micro/nano-patterning technique,which is a high-resolution,high-throughput and yet simple fabrication process.According to International Technology Roadmap for Semiconductor...Nanoimprint lithography(NIL) is an emerging micro/nano-patterning technique,which is a high-resolution,high-throughput and yet simple fabrication process.According to International Technology Roadmap for Semiconductor(ITRS),NIL has emerged as the next generation lithography candidate for the22 nm and 16 nm technological nodes.In this paper,we present an overview of nanoimprint lithography.The classfication,research focus,critical issues,and the future of nanoimprint lithography are intensively elaborated.A pattern as small as 2.4 nm has been demonstrated.Full-wafer nanoimprint lithography has been completed on a 12-inch wafer.Recently,12.5 nm pattern resolution through soft molecular scale nanoimprint lithography has been achieved by EV Group,a leading nanoimprint lithography technology supplier.展开更多
Nanoimprint lithography (NIL) is recognized as one of the most promising candidates for the next generation lithography (NGL) to obtain sub-100 nm patterns because of its simplicity, high-throughput and low-cost. Whil...Nanoimprint lithography (NIL) is recognized as one of the most promising candidates for the next generation lithography (NGL) to obtain sub-100 nm patterns because of its simplicity, high-throughput and low-cost. While substantial effort has been expending on NIL for producing smaller and smaller feature sizes, considerably less effort has been devoted to the equally important issue—alignment between template and substrate. A homemade prototype nanoimprint lithography tool with a high precision automatic alignment system based on Moiré signals is presented. Coarse and fine pitch gratings are adopted to produce Moiré signals to control macro and micro actuators and enable the substrate to move towards the desired position automatically. Linear motors with 300 mm travel range and 1 μm step resolution are used as macro actuators, and piezoelectric translators with 50 μm travel range and 1 nm step resolution are used as micro actuators. In addition, the prototype provides one translation (z displacement) and two tilting motion(α and β ) to automatically bring uniform intact contact between the template and substrate surfaces by using a flexure stage. As a result, 10 μm coarse alignment accuracy and 20 nm fine alignment accuracy can be achieved. Finally, some results of nanostructures and micro devices such as nanoscale trenches and holes, gratings and microlens array fabricated using the prototype tool are presented, and hot embossing lithography, one typical NIL technology, are depicted by taking nanoscale gratings fabrication as an example.展开更多
To tackle the demoulding and conglutinating problem with the resist and hard mold in the nanoimprint lithography process, a soft mould can be used to demould and reduce the macro or mi- cro mismatch between mould bott...To tackle the demoulding and conglutinating problem with the resist and hard mold in the nanoimprint lithography process, a soft mould can be used to demould and reduce the macro or mi- cro mismatch between mould bottom surface and wafer top surface. In nanoimprint lithography process, a mathematical equation is formulated to demonstrate the relation between the residual re- sist thickness and the pressing force during pressing the mould toward the resist-coated wafer. Based on these analytical studies, a new imprint process, which includes a pre-cure release of the pressing force, was proposed for the high-conformity transfer of nano-patterns from the mould to the wafer. The results of a series of imprint experiments showed that the proposed loading process could meet the requirements for the imprint of different patterns and feature sizes while maintaining a uniform residual resist and non-distorted transfer of nano-patterns from the mould to the resist- coated wafer.展开更多
Technology roadmaps have been a part of the semiconductor industry for many years.The first roadmap was Moore’s law,which started as an empirical observation that competitive forces then turned into a prediction that...Technology roadmaps have been a part of the semiconductor industry for many years.The first roadmap was Moore’s law,which started as an empirical observation that competitive forces then turned into a prediction that became an industry roadmap.Then the ITRS roadmap was developed and for many years was used by leading edge semiconductor producers to drive new technology they needed.Now there is the IRDS roadmap,which projects semiconductor end user requirements and develops a technology roadmap based on those requirements.The 2017 IRDS roadmap was just released.To prepare the roadmap,we received input from experts around the world.The roadmap predicts that the requirements of high performance logic will drive the development of different device structures in logic chips.Memory technology will also advance but is more focused on cost than high performance logic is.Because of this,there may be a split in the patterning roadmaps for different types of devices.Logic will adopt EUV and its extensions,while flash memory will consider nanoimprint.Directed self-assembly and direct write e-beam are also being developed.DSA has the potential to improve CD uniformity and lower costs.Direct write e-beam promises to make personalization of chips more feasible.DRAM memory will trail logic in critical dimensions and will adopt EUV when it becomes cost effective.The lithography community will both have to make EUV work and overcome the challenges of randomness in CDs and resist performance,while memory will try to make nanoimprint a reliable and low defect method of patterning.Long term,logic is expected to start focusing on 3D architectures in the late 2020’s.This will put a tremendous stress on the yield of patterning processes and on reducing the number of process steps that are required.It will also put more focus on hole type patterns,which will become one of the key patterning challenges in the future.展开更多
We report herein a rational approach for fabricating metal suspending nanostructures by nanoimprint lithography(NIL) and isotropic reactive ion etching(RIE).The approach comprises three principal steps:(1) mold fabric...We report herein a rational approach for fabricating metal suspending nanostructures by nanoimprint lithography(NIL) and isotropic reactive ion etching(RIE).The approach comprises three principal steps:(1) mold fabrication,(2) structure replication by NIL,and(3) suspending nanostructures creation by isotropic RIE.Using this approach,suspending nanostructures with Au,Au/Ti or Ti/Au bilayers,and Au/Ti/Au sandwiched structures are demonstrated.For Au nanostructures,straight suspending nanostructures can be obtained when the thickness of Au film is up to 50 nm for nano-bridge and 90 nm for nano-finger patterns.When the thickness of Au is below 50 nm for nano-bridge and 90 nm for nano-finger,the Au suspending nanostructures bend upward as a result of the mismatch of thermal expansion between the thin Au films and Si substrate.This leads to residual stresses in the thin Au films.For Au/Ti or Ti/Au bilayers nanostructures,the cantilevers bend toward Au film,since Au has a larger thermal expansion coefficient than that of Ti.While in the case of sandwich structures,straight suspending nanostructures are obtained,this may be due to the balance of residual stress between the thin films.展开更多
基金supported by Natural Science Foundation of Shanghai(No.11ZR1432100)Shanghai Postdoctoral Science Foundation(11R21420900)
文摘Nanoimprint lithography(NIL) is an emerging micro/nano-patterning technique,which is a high-resolution,high-throughput and yet simple fabrication process.According to International Technology Roadmap for Semiconductor(ITRS),NIL has emerged as the next generation lithography candidate for the22 nm and 16 nm technological nodes.In this paper,we present an overview of nanoimprint lithography.The classfication,research focus,critical issues,and the future of nanoimprint lithography are intensively elaborated.A pattern as small as 2.4 nm has been demonstrated.Full-wafer nanoimprint lithography has been completed on a 12-inch wafer.Recently,12.5 nm pattern resolution through soft molecular scale nanoimprint lithography has been achieved by EV Group,a leading nanoimprint lithography technology supplier.
基金This project is supported by National Hi-tech Research and Development Program of China (863 Program, No. 2002AA404430)National Natural Science Foundation of China (No. 50475137).
文摘Nanoimprint lithography (NIL) is recognized as one of the most promising candidates for the next generation lithography (NGL) to obtain sub-100 nm patterns because of its simplicity, high-throughput and low-cost. While substantial effort has been expending on NIL for producing smaller and smaller feature sizes, considerably less effort has been devoted to the equally important issue—alignment between template and substrate. A homemade prototype nanoimprint lithography tool with a high precision automatic alignment system based on Moiré signals is presented. Coarse and fine pitch gratings are adopted to produce Moiré signals to control macro and micro actuators and enable the substrate to move towards the desired position automatically. Linear motors with 300 mm travel range and 1 μm step resolution are used as macro actuators, and piezoelectric translators with 50 μm travel range and 1 nm step resolution are used as micro actuators. In addition, the prototype provides one translation (z displacement) and two tilting motion(α and β ) to automatically bring uniform intact contact between the template and substrate surfaces by using a flexure stage. As a result, 10 μm coarse alignment accuracy and 20 nm fine alignment accuracy can be achieved. Finally, some results of nanostructures and micro devices such as nanoscale trenches and holes, gratings and microlens array fabricated using the prototype tool are presented, and hot embossing lithography, one typical NIL technology, are depicted by taking nanoscale gratings fabrication as an example.
基金Supported by National Natural Science Foundation of China (No. E05020203) , "863" National Hi-Tech Program(No.2002AA420050) and "973" National Key Basic Research Program ( No. 2003CB716202).
文摘To tackle the demoulding and conglutinating problem with the resist and hard mold in the nanoimprint lithography process, a soft mould can be used to demould and reduce the macro or mi- cro mismatch between mould bottom surface and wafer top surface. In nanoimprint lithography process, a mathematical equation is formulated to demonstrate the relation between the residual re- sist thickness and the pressing force during pressing the mould toward the resist-coated wafer. Based on these analytical studies, a new imprint process, which includes a pre-cure release of the pressing force, was proposed for the high-conformity transfer of nano-patterns from the mould to the wafer. The results of a series of imprint experiments showed that the proposed loading process could meet the requirements for the imprint of different patterns and feature sizes while maintaining a uniform residual resist and non-distorted transfer of nano-patterns from the mould to the resist- coated wafer.
文摘Technology roadmaps have been a part of the semiconductor industry for many years.The first roadmap was Moore’s law,which started as an empirical observation that competitive forces then turned into a prediction that became an industry roadmap.Then the ITRS roadmap was developed and for many years was used by leading edge semiconductor producers to drive new technology they needed.Now there is the IRDS roadmap,which projects semiconductor end user requirements and develops a technology roadmap based on those requirements.The 2017 IRDS roadmap was just released.To prepare the roadmap,we received input from experts around the world.The roadmap predicts that the requirements of high performance logic will drive the development of different device structures in logic chips.Memory technology will also advance but is more focused on cost than high performance logic is.Because of this,there may be a split in the patterning roadmaps for different types of devices.Logic will adopt EUV and its extensions,while flash memory will consider nanoimprint.Directed self-assembly and direct write e-beam are also being developed.DSA has the potential to improve CD uniformity and lower costs.Direct write e-beam promises to make personalization of chips more feasible.DRAM memory will trail logic in critical dimensions and will adopt EUV when it becomes cost effective.The lithography community will both have to make EUV work and overcome the challenges of randomness in CDs and resist performance,while memory will try to make nanoimprint a reliable and low defect method of patterning.Long term,logic is expected to start focusing on 3D architectures in the late 2020’s.This will put a tremendous stress on the yield of patterning processes and on reducing the number of process steps that are required.It will also put more focus on hole type patterns,which will become one of the key patterning challenges in the future.
基金Supported by the National Natural Science Foundation of China (Grant No. 20573002)the Major State Basic Research Development Program of China (973Pprogram) (Grant No. 2001CB6105)
文摘We report herein a rational approach for fabricating metal suspending nanostructures by nanoimprint lithography(NIL) and isotropic reactive ion etching(RIE).The approach comprises three principal steps:(1) mold fabrication,(2) structure replication by NIL,and(3) suspending nanostructures creation by isotropic RIE.Using this approach,suspending nanostructures with Au,Au/Ti or Ti/Au bilayers,and Au/Ti/Au sandwiched structures are demonstrated.For Au nanostructures,straight suspending nanostructures can be obtained when the thickness of Au film is up to 50 nm for nano-bridge and 90 nm for nano-finger patterns.When the thickness of Au is below 50 nm for nano-bridge and 90 nm for nano-finger,the Au suspending nanostructures bend upward as a result of the mismatch of thermal expansion between the thin Au films and Si substrate.This leads to residual stresses in the thin Au films.For Au/Ti or Ti/Au bilayers nanostructures,the cantilevers bend toward Au film,since Au has a larger thermal expansion coefficient than that of Ti.While in the case of sandwich structures,straight suspending nanostructures are obtained,this may be due to the balance of residual stress between the thin films.
