Preparation, structural and electrical properties of zinc oxide grown on silicon nanoporous pillar array

Polycrystalline thick film of zinc oxide （ZnO） is grown on a unique silicon substrate with a hierarchical structure, silicon nanoporous pillar array （Si-NPA）, by using a vapour phase transport method. It is found that as-grown ZnO film is composed of closely packed ZnO crystallites with an average size of -10 μm. The film resistivity of ZnO/SiNPA is measured to be -8.9Ωcm by the standard four probe method. The lengthwise Ⅰ-Ⅴ curve of ZnO/Si-NPA heterostructure is measured. Theoretical analysis shows that the carrier transport across ZnO/Si-NPA heterojunction is dominated by two mechanisms, i.e. a thermionic process at high voltages and a quantum tunnelling process at low voltages.

Time-Resolved Photoluminescence Study of Silicon Nanoporous Pillar Array

A silicon nanoporous pillar array （Si-NPA） is thought to be a promising functional substrate for constructing a variety of Si-based optoelectronic nanodevices, due to its unique hierarchical structure and enhanced physical properties. This makes the in-depth understanding of the photoluminescence （PL） of Si-NPA crucial for both scientific research and practical applications. In this work, the PL properties of Si-NPA are studied by measuring both the steady-state and time-resolved PL spectrum. Based on the experimental data, the three PL bands of Si-NPA, i.e., the ultraviolet band, the purple-blue plateau and the red band are assigned to the oxygen-excess defects in Si oxide or silanol groups at the surface of Si nanocrystallites （nc-Si）, oxygen deficiency defects in Si oxide, and band-to-band transition of nc-Si under the frame of quantum confinement combining with the surface states like Si=O and Si-O^i bonds at the surface of nc-Si, respectively. These results may provide some novel insight into the PL process of Si-NPA and may be helpful for clarifying the PL mechanism.

Achieving a sub-10 nm nanopore array in silicon by metal-assisted chemical etching and machine learning

Solid-state nanopores with controllable pore size and morphology have huge application potential.However,it has been very challenging to process sub-10 nm silicon nanopore arrays with high efficiency and high quality at low cost.In this study,a method combining metal-assisted chemical etching and machine learning is proposed to fabricate sub-10 nm nanopore arrays on silicon wafers with various dopant types and concentrations.Through a SVM algorithm,the relationship between the nanopore structures and the fabrication conditions,including the etching solution,etching time,dopant type,and concentration,was modeled and experimentally verified.Based on this,a processing parameter window for generating regular nanopore arrays on silicon wafers with variable doping types and concentrations was obtained.The proposed machine-learning-assisted etching method will provide a feasible and economical way to process high-quality silicon nanopores,nanostructures,and devices.

Forward and reverse electron transport properties across a CdS/Si multi-interface nanoheterojunction

The electron transport behavior across the interface plays an important role in determining the performance of op- toelectronic devices based on heterojunctions. Here through growing CdS thin film on silicon nanoporous pillar array, an untraditional, nonplanar, and multi-interface CdS/Si nanoheterojunction is prepared. The current density versus voltage curve is measured and an obvious rectification effect is observed. Based on the fitting results and model analyses on the forward and reverse conduction characteristics, the electron transport mechanism under low forward bias, high forward bias, and reverse bias are attributed to the Ohmic regime, space-charge-limited current regime, and modified Poole-Frenkel regime respectively. The forward and reverse electrical behaviors are found to be highly related to the distribution of inter- facial trap states and the existence of localized electric field respectively. These results might be helpful for optimizing the preparing procedures to realize high-performance silicon-based CdS optoelectronic devices.