A single-photon fault-detection method for nanocircuits that use GaN material

As the complexity of nanocircuits continues to increase,developing tests for them becomes more difficult.Failure analysis and the localization of internal test points within nanocircuits are already more difficult than for conventional integrated circuits.In this paper,a new method of testing for faults in nanocircuits is presented that uses single-photon detection to locate failed components(or failed signal lines)by utilizing the infrared photon emission characteristics of circuits.The emitted photons,which can carry information about circuit structure,can aid the understanding of circuit properties and locating faults.In this paper,in order to enhance the strength of emitted photons from circuit components,test vectors are designed for circuits’components or signal lines.These test vectors can cause components to produce signal transitions or switching behaviors according to their positions,thereby increasing the strength of the emitted photons.A multiple-valued decision diagram(MDD),in the form of a directed acrylic graph,is used to produce the test vectors.After an MDD corresponding to a circuit is constructed,the test vectors are generated by searching for specific paths in the MDD of that circuit.Experimental results show that many types of faults such as stuck-at faults,bridging faults,crosstalk faults,and others,can be detected with this method.

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

The double gate （DG） silicon MOSFET with an extremely short-channel length has the appropriate fea- tures to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill meth- ods and models in terms of their complexity and computation time （self-consistent, quantum computations ）. Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic cir- cuit design. The approach is general and thus is suitable for any type ofnanoscale structure investigation problems in the nanotechnology industry.

High accuracy digital aging monitor based on PLL-VCO circuit

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator（PLL-VCO） circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28×298.94 μm^2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.