Simulations of backgate sandwich nanowire MOSFETs with improved device performance

We propose a novel backgate sandwich nanowire MOSFET （SNFET）, which offers the advantages of ETSOI （dynamic backgate voltage controllability） and nanowire FETs （good short channel effect）. A backgate is used for threshold voltage （Vt） control of the SNFET. Compared with a backgate FinFET with a punch-through stop layer （PTSL）, the SNFET possesses improved device performance. 3D device simulations indicate that the SNFET has a three times larger overdrive current, a -75% smaller off leakage current, and reduced subthreshold swing （SS） and DIBL than those of a backgate FinFET when the nanowire （NW） and the fin are of equal width. A new process flow to fabricate the backgate SNFET is also proposed in this work. Our analytical model suggests that Vt control by the backgate can be attributed to the capacitances formed by the frontgate, NW, and backgate. The SNFET devices are compatible with the latest state-of-the-art high-k/metal gate CMOS technology with the unique capability of independent backgate control for nFETs and pFETs, which is promising for sub-22 nm scaling down.

Capacitance extraction method for a gate-induced quantum dot in silicon nanowire metal-oxide-semiconductor field-effect transistors

An improved method of extracting the coupling capacitances of quantum dot structure is reported. This method is based on measuring the charge transfer current in the silicon nanowire metal-oxide-semiconductor field-effect transistor （MOSFET）, in which the channel closing and opening are controlled by applying alternating-current biases with a half period phase shift to the dual lower gates. The capacitances around the dot, including fringing capacitances and barrier capacitances, are obtained by analyzing the relation between the transfer current and the applied voltage. This technique could be used to extract the capacitance parameters not only from the bulk silicon devices, but also from the silicon-on-insulator （SOI） MOSFETs.

An oxide/silicon core/shell nanowire metal-oxide semiconductor field-effect transistor

This paper studies an oxide/silicon core/shell nanowire MOSFET （OS-CSNM）. Through three-dimensional device simulations, we have demonstrated that the OS-CSNM has a lower leakage current and higher Ion/Ioff ratio after intro- ducing the oxide core into a traditional nanowire MOSFET （TNM）. The oxide/silicon OS-CSNM structure suppresses threshold voltage roll-off, drain induced barrier lowering and subthreshold swing degradation. Smaller intrinsic device delay is also observed in OS-CSNM in comparison with that of TNM.