CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Sliding-mode Observer-based Grid Voltage-observation Method with Frequency-fixed Dual SOGI and Cross-compensated Phase-locked Loop

Conventional sliding-mode observer(SMO)-based grid-voltage observation methods often require a low-pass filter(LPF)to remove high-frequency sliding-mode noise.However,a complicated phase-and amplitude-compensation method,which is highly sensitive to the DC-offset,is required.A frequency-adaptive dual second-order generalized integrator(SOGI)can be used to replace the LPF,eliminating the compensation link and the effects of the DC-offset;however,strong coupling is introduced between the front-end SOGI block and back-end phase-locked loop(PLL)block,thereby reducing the dynamic performance.To solve this problem,this study proposes an SMO-based grid-voltage observation method with a frequency-fixed dual SOGI and cross-compensated PLL that can eliminate the frequency coupling between the front-end SOGI block and back-end PLL blocks,thereby increasing its dynamic performance.In this study,the phase and amplitude are compensated simultaneously using the proposed cross-compensation method,achieving an accurate observation of the grid voltage under off-nominal frequencies.An analysis of the small-signal model theoretically verified that the proposed method has good dynamic performance.Finally,the superiority of the proposed method is verified through comparative experiments.

Design and implementation of digital closed-loop drive control system of a MEMS gyroscope

In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.

Small-signal Stability Analysis and Improvement with Phase-shift Phase-locked Loop Based on Back Electromotive Force Observer for VSC-HVDC in Weak Grids

Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.

Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art

This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.

Tracking error analysis and simulation of FLL-assisted PLL

In order to solve problems in high dynamic environment, a frequency-locked loop （FLL） assisted phase-locked loop （PLL） is put forward for carrier tracking. On the basis of the analysis of discriminators, the total phase error of the tracking loop is analyzed and a general error expression is derived. By using linearization and Jaffe-Rechtin coefficients, the performance of a special first order FLL-assisted second order PLL is analyzed to get a closed expression. Analysis results and simula- tions show that there exist an optimal FLL loop bandwidth and a optimal PLL loop bandwidth which can make the phase jitter much less than that when the PLL is used alone.

Sensorless Control of Permanent Magnet Synchronous Motor Based on New Sliding Mode Observer with Single Resistor Current Reconstruction

To solve the chattering problem caused by discontinuous switching function in traditional sliding mode observer,a piecewise square root switching function with continuously varying characteristics is designed,and its stability is analyzed by using Lyapunov stability criterion.Secondly,according to the relationship among bus current,switching state and phase current,a single bus resistance sampling current reconstruction scheme without current sensors is adopted,which effectively reduces the cost of motor system.Finally,the feasibility and effectiveness of the proposed scheme are verified by simulation.

Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.

Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable G_m-C loop filter

This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.

Comparative Study of Single-phase Phase-locked Loops for Grid-connected Inverters Under Non-ideal Grid Conditions

In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.

2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS

The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.

一种新颖的无传感器异步电动机直接转矩控制系统

磁链的准确估计是无传感器直接转矩控制系统的关键,本文提出了新型改进低通滤波器和PLL锁相环技术相结合的磁链估计新方法。该方法提高了定子磁链的估计精度,改善了无传感器异步电动机直接转矩控制系统的动静态性能。仿真结果和实验结果表明了基于新方法的无传感器直接转矩控制系统的良好动静态性能及其对定子电阻的鲁棒性。

Design of beacon system based on MSP430 micro- controller

In order to solve the onboard recorder search problem, a new beacon system based on radio direction finding tech- nique, which indicates the orientation of the recorder, is designed. The system consists of phase-locked loop （PLL）, micro- processor, global position system （GPS） module, power module and so on. The scene simulation verifies the feasibility and reliability of the system. This beacon system can be applied to the recorder search in many fields, and can effectively reduce the search scope and improve work efficiency.

微弱信号检测与锁定放大电路

介绍了一种微弱信号的检测与锁定放大方法。通过模拟锁相环工作锁定待检微弱信号的频率,利用控制器测量该锁相环的输出频率,并根据该频率值控制直接数字合成电路产生同频信号,该信号作为相关检测所需的参考信号。系统采用乘法器和积分电路实现相关检测,通过步进调整参考信号的相位,使互相关值最大,获得与被测信号同频同相的再生信号,从而实现微弱信号的检测与放大。该方法能够实现频率检测及幅度检测等功能。经实验测试表明:在低信噪比条件下,该方法仍具有较好的线性测量特性和较高的准确度,可实现任意波形的微弱信号自动检测和再生放大。

基于新型锁相环的水下推进永磁同步电机无位置传感器控制

针对水下推进永磁同步电机无位置传感器控制中,基于传统锁相环的龙伯格观测器无法同时处理永磁同步电机正向和反向运行所带来的转子位置误差问题,本文提出了一种基于新型锁相环的龙伯格观测器水下推进器转子位置辨识方法。该方法在双闭环矢量控制系统的基础上,先由龙伯格观测器估算电机的反电动势,再将反电动势作为新型锁相环的输入,在所设计的新型锁相环中,鉴相器模块是实际转子位置与估计转子位置间的比较环节,压控振荡器模块将转速积分得到转子位置,环路滤波器模块是PI调节,最终由锁相环辨识转子位置和速度。仿真结果表明,该方法较传统锁相环在转子位置方面具有较高的辨识精度、能够实现永磁同步电机在正向和反向工况下转子位置误差均可收敛的功能。

永磁直驱风电变流器无传感器控制研究

永磁直驱风力发电系统是一种新型的风力发电系统,具有广泛的应用前景。背靠背的全功率变流器是直驱型风力发电系统中的关键设备,既要实现对电网转换优质电能的功能,又要对永磁同步发电机(PMSG)进行控制。永磁同步发电机的无传感器控制技术具有重要的研究意义。根据永磁同步发电机的数学模型,利用其电磁、电气关系,提出了一种基于转子磁链闭环锁相环的永磁同步发电机位置的估算算法。通过仿真和实验结果表明,利用该估算方法能够准确计算出永磁同步发电机的位置,并可以利用其对永磁同步发电机实现有效的控制。

A High-Speed Dual Modulus Prescaler Using 0.25 μm CMOS Technology

A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.

Transient Stability Analysis of Grid-connected Converters in Wind Turbine Systems Based on Linear Lyapunov Function and Reverse-time Trajectory

As the proportion of converter-interfaced renewable energy resources in the power system is increasing,the strength of the power grid at the connection point of wind turbine generators(WTGs)is gradually weakening.Existing research has shown that when connected with the weak grid,the stability of the traditional grid-following controlled converters will deteriorate,and they are prone to unstable phenomena such as oscillation.Due to the limitations of linear analysis that cannot sufficiently capture the stability phenomena,transient stability must be investigated.So far,standalone time-domain simulations or analytical Lyapunov stability criteria have been used to investigate transient stability.However,the time-domain simulations have proven to be computationally too heavy,while analytical methods are difficult to formulate for larger systems,require many modelling assumptions,and are often conservative in estimating the stability boundary.This paper proposes and demonstrates an innovative approach to estimating the transient stability boundary via combining the linear Lyapunov function and the reverse-time trajectory technique.The proposed methodology eliminates the need of time-consuming simulations and the conservative nature of Lyapunov functions.This study brings out the clear distinction between the stability boundaries with different post-fault active current ramp rate controls.At the same time,it provides a new perspective on critical clearing time for wind turbine systems.The stability boundary is verified using time-domain simulation studies.

Simulation of Analog Costas Loop Circuits

The analysis of stability and numerical simulation of Costas loop circuits for the high-frequency signals is a challenging task. The problem lies in the fact that it is necessary to observe very fast time scale of input signals and slow time scale of signal s phases simultaneously. To overcome this difficulty, it is possible to follow the classical ideas of Gardner and Viterbi to construct a mathematical model of Costas loop, in which only slow time change of signal s phases and frequencies is considered. Such an construction, in turn,requires the computation of phase detector characteristic, depending on the waveforms of the considered signals. In this paper, the problems of nonlinear analysis of Costas loops and the approaches to the simulation of the classical Costas loop, the quadrature phase shift keying(QPSK) Costas loop, and the two-phase Costas loop are discussed. The analytical method for the computation of phase detector characteristics of Costas loops is described.