Gigahertz frequency hopping in an optical phase-locked loop for Raman lasers

Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.

Vein visualization enhancement by dual-wavelength phase-locked denoising technology

Visual near-infrared imaging equipment has broad applications in various fields such as venipuncture,facial injections,and safety verification due to its noncontact,compact,and portable design.Currently,most studies utilize near-infrared single-wavelength for image acquisition of veins.However,many substances in the skin,including water,protein,and melanin can create significant background noise,which hinders accurate detection.In this paper,we developed a dual-wavelength imaging system with phase-locked denoising technology to acquire vein image.The signals in the effective region are compared by using the absorption valley and peak of hemoglobin at 700nm and 940nm,respectively.The phase-locked denoising algorithm is applied to decrease the noise and interference of complex surroundings from the images.The imaging results of the vein are successfully extracted in complex noise environment.It is demonstrated that the denoising effect on hand veins imaging can be improved with 57.3%by using our dual-wavelength phase-locked denoising technology.Consequently,this work proposes a novel approach for venous imaging with dual-wavelengths and phase-locked denoising algorithm to extract venous imaging results in complex noisy environment better.

11.6-GHz 0.18-μm monolithic CMOS phase-locked loop

A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.

A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock's stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

Rapid and stable calcium-looping solar thermochemical energy storage via co-doping binary sulfate and Al–Mn–Fe oxides

Solar thermochemical energy storage based on calcium looping(CaL)process is a promising technology for next-generation concentrated solar power(CSP)systems.However,conventional calcium carbonate(CaCO_(3))pellets suffer from slow reaction kinetics,poor stability,and low solar absorptance.Here,we successfully realized high power density and highly stable solar thermochemical energy storage/release by synergistically accelerating energy storage/release via binary sulfate and promoting cycle stability,mechanical strength,and solar absorptance via Al–Mn–Fe oxides.The energy storage density of proposed CaCO_(3)pellets is still as high as 1455 kJ kg^(-1)with only a slight decay rate of 4.91%over 100 cycles,which is higher than that of state-of-the-art pellets in the literature,in stark contrast to 69.9%of pure CaCO_(3)pellets over 35 cycles.Compared with pure CaCO_(3),the energy storage power density or decomposition rate is improved by 120%due to lower activation energy and promotion of Ca^(2+)diffusion by binary sulfate.The energy release or carbonation rate rises by 10%because of high O^(2-)transport ability of molten binary sulfate.Benefiting from fast energy storage/release rate and high solar absorptance,thermochemical energy storage efficiency is enhanced by more than 50%under direct solar irradiation.This work paves the way for application of direct solar thermochemical energy storage techniques via achieving fast energy storage/release rate,high energy density,good cyclic stability,and high solar absorptance simultaneously.

量子Loop代数U_(q)(L(sl_(2)))的单权模

用构造的方法解决量子Loop代数U_(q)(L(sl_(2)))具有一个一维权空间的单权模的结构问题,得到了任意一个具有一维权空间的单权模必同构于U_(q)(L(sl_(2)))的四类单权模之一.此外,还构造了一类权空间维数为2的既非最高权也非最低权的量子Loop代数U_(q)(L(sl_(2)))的单权模.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Advancing neuroscience through real-time processing of big data:Transition from open-loop to closed-loop paradigms

The brain functions as a closed-loop system that continuously generates behavior in response to the external environment and adjusts actions based on the outcomes.Traditional research methodologies in neuroscience,especially those employed in brain imaging experiments,have mainly adopted an open-loop paradigm(Grosenick et al.,2015).Functional neural circuits are analyzed offline and subsequently tested through manipulation of neuronal activities within specific regions or with genetic markers.By establishing a closed-loop research paradigm,functional ensembles can be detected and tested in real time with temporal sequences.These functional ensembles,rather than brain regions or genetically labeled neural populations,serve as fundamental units of neural networks,offering valuable insights into the dissection of neural circuits.The closed-loop research paradigm also enables the capture of high-dimensional activities of internal brain dynamics and precise elucidation of physiological processes such as learning,decision-making,and sleep.

庆阳驴mtDNA D-loop区遗传多样性及起源分析

[目的]研究庆阳驴养殖群体的遗传多样性与母系起源,了解其遗传信息,为保护庆阳驴种质资源、选育和遗传改良工作提供理论依据。[方法]随机选取133头庆阳驴,对其线粒体DNA(mitochondrial DNA,mtDNA)D-loop区序列进行PCR扩增、测序及比对,并探讨庆阳驴的遗传多样性与母系起源。[结果]在获得的520 bp D-loop碱基序列中,AT含量(57.3%)高于GC含量(42.8%),表现出碱基的偏倚性;检测到38个变异位点,包含8个碱基对的转换;其核苷酸多样性(Pi)、单倍型多样性(Hd)、平均核苷酸差异(K)分别为0.01591、0.895和8.274,与欧洲家驴和中国家驴研究的平均值相比较低,说明该驴品种核苷酸变异较为贫乏。庆阳驴mtDNA D-loop区存在35个单倍型,单倍型之间的遗传距离为0.002~0.042。系统进化结果显示,庆阳驴存在2个线粒体支系,表明其具有2个母系起源,且遗传距离表明,庆阳驴与克罗地亚家驴之间的遗传距离较近。[结论]本研究从分子水平初步揭示庆阳驴核苷酸变异比较贫乏,杂交程度高,mtDNA遗传多态性正逐步丧失,应加强庆阳驴品种的遗传资源保护工作。

Mn-doped SrCoO_(3-δ) Perovskite Oxides for Ethylene Production via Chemical Looping Oxidative Dehydrogenation of Ethane

Chemical looping oxidative dehydrogenation (CL-ODH) is an economically promising method for convertingethane into higher value-added ethylene utilizing lattice oxygen in redox catalysts, also known as oxygen carriers. Inthis study, perovskite-type oxide SrCoO_(3-δ) and B-site Mn ion-doped oxygen carriers (SrCo_(1-x)MnxO_(3-δ), x=0.1, 0.2, 0.3)were prepared and tested for the CL-ODH of ethane. The oxygen-deficient perovskite SrCoO_(3-δ) exhibited high ethyleneselectivity of up to 96.7% due to its unique oxygen vacancies and lattice oxygen migration rates. However, its low ethyleneyield limits its application in the CL-ODH of ethane. Mn doping promoted the reducibility of SrCoO_(3-δ) oxygen carriers,thereby improving ethane conversion and ethylene yield, as demonstrated by characterization and evaluation experiments.X-ray diffraction results confirmed the doping of Mn into the lattice of SrCoO_(3-δ), while X-ray photoelectron spectroscopy(XPS) indicated an increase in lattice oxygen ratio upon incorporation of Mn into the SrCoO_(3-δ) lattice. Additionally, H2temperature-programmed reduction (H2-TPR) tests revealed more peaks at lower temperature reduction zones and a declinein peak positions at higher temperatures. Among the four tested oxygen carriers, SrCo0.8Mn0.2O_(3-δ) exhibited satisfactoryperformance with an ethylene yield of 50% at 710 °C and good stability over 20 redox cycles. The synergistic effect of Mnplays a key role in increasing ethylene yields of SrCoO_(3-δ) oxygen carriers. Accordingly, SrCo0.8Mn0.2O_(3-δ) shows promisingpotential for the efficient production of ethylene from ethane via CL-ODH.

基于D-loop序列和微卫星标记的4个黄颡鱼群体的遗传变异分析

为探究广东珠江、广西漓江、四川金沙江和云南西江4个水系黄颡鱼(Pelteobagrus fulvidraco)群体的遗传变异情况,本研究分别基于上述水系共108尾黄颡鱼的线粒体D-loop序列和12个微卫星标记对4个黄颡鱼群体进行群体内遗传多样性、群体间遗传距离和变异及群体结构分析。结果表明:共得到105个D-loop序列,其核苷酸组成中A+T含量占比为56.22%,G+C含量占比为43.78%。在105个有效序列中,多态位点数为746个(含缺和无效多态位点),单倍型数为51个。Hap2、Hap25、Hap15分别是广东珠江、广西漓江、四川金沙江群体的优势单倍型。4个黄颡鱼群体的单倍型多样性(H_(d))介于0.842~0.940,核苷酸多样性(π)介于0.002~0.083;四川金沙江群体Hd的最低,π也处于较低水平;而云南西江群体的Hd和π均最高;4个群体的Tajima′s D值均小于0。等位基因数(Na)、有效等位基因数(Ne)、观测杂合度(Ho)、期望杂合度(He)、多态信息含量(PIC)均为广西漓江群体最高,广东珠江群体次之,云南西江群体较低,四川金沙江群体最低。4个黄颡鱼群体的K2P遗传距离介于0.008~0.115之间,其中广西漓江与云南西江群体间的K2P遗传距离最近;广东珠江群体与其他3个群体的K2P遗传距离较远,与四川金沙江群体的K2P遗传距离最远。4个黄颡鱼群体间均存在极显著的遗传分化(P<0.01),群体间遗传分化指数(F_(st))介于0.114~0.959之间。4个黄颡鱼群体间Nei’s遗传距离和遗传一致性分别介于0.117~1.114之间和0.328~0.890之间,其中,广西漓江群体与云南西江群体的Nei’s遗传距离最近、遗传一致性最高,广东珠江与四川金沙江群体的Nei’s遗传距离最远、遗传一致性最低。在UPGMA系统聚类树中,4个黄颡鱼群体主要分为两支,其中广西漓江群体、云南西江群体最先聚为一支,然后与四川金沙江群体聚为一支,最后与广东珠江群体聚类。在NJ聚类树中,4个群体黄颡鱼的明显分为4个分支,广西漓江群体与云南西江群体呈镶嵌式分布。4个黄颡鱼群体中共享单倍型较少,但特有单倍型较多,其中云南西江和广西漓江群体相邻较近且共有单倍型较多。在基于Nei’s遗传距离进行的主坐标分析中,广西漓江群体和云南西江群体的个体之间遗传差异较小,广东珠江和四川金沙江群体的个体之间遗传差异较大。说明四川金沙江群体遗传多样性水平较低,云南西江群体遗传多样性水平较高,广西漓江群体与云南西江群体存在一定的基因交流。

Age of Loop Information with Flexible Transmission Enabled Communication and Control Co-Design in Industrial IoT

Precise and low-latency information transmission through communication systems is essential in the Industrial Internet of Things(IIoT).However,in an industrial system,there is always a coupling relationship between the control and communication components.To improve the system's overall performance,exploring the co-design of communication and control systems is crucial.In this work,we propose a new metric±Age of Loop Information with Flexible Transmission(AoLI-FT),which dynamically adjusts the maximum number of uplink(UL)and downlink(DL)transmission rounds,thus enhancing reliability while ensuring timeliness.Our goal is to explore the relationship between AoLI-FT,reliability,and control convergence rate,and to design optimal blocklengths for UL and DL that achieve the desired control convergence rate.To address this issue,we first derive a closed-form expression for the upper bound of AoLI-FT.Subsequently,we establish a relationship between communication reliability and control convergence rates using a Lyapunov-like function.Finally,we introduce an iterative alternating algorithm to determine the optimal communication and control parameters.The numerical results demonstrate the significant performance advantages of our proposed communication and control co-design strategy in terms of latency and control cost.

Optimizing the sulfur-resistance and activity of perovskite oxygen carrier for chemical looping dry reforming of methane

Perovskite oxides has been attracted much attention as high-performance oxygen carriers for chemical looping reforming of methane,but they are easily inactivated by the presence of trace H_(2)S.Here,we propose to modulate both the activity and resistance to sulfur poisoning by dual substitution of Mo and Ni ions with the Fe-sites of LaFeO_(3)perovskite.It is found that partial substitution of Ni for Fe substantially improves the activity of LaFeO_(3)perovskite,while Ni particles prefer to grow and react with H_(2)S during the long-term successive redox process,resulting in the deactivation of oxygen carriers.With the presence of Mo in LaNi_(0.05)Fe_(0.95)O_(3−σ)perovskite,H_(2)S preferentially reacts with Mo to generate MoS_(2),and then the CO_(2)oxidation can regenerate Mo via removing sulfur.In addition,Mo can inhibit the accumulation and growth of Ni,which helps to improve the redox stability of oxygen carriers.The LaNi_(0.05)Mo_(0.07)Fe_(0.88)O_(3−σ)oxygen carrier exhibits stable and excellent performance,with the CH_(4)conversion higher than 90%during the 50 redox cycles in the presence of 50 ppm H_(2)S at 800℃.This work highlights a synergistic effect in the perovskite oxides induced by dual substitution of different cations for the development of high-performance oxygen carriers with excellent sulfur tolerance.

Effects of interstitial cluster mobility on dislocation loops evolution under irradiation of austenitic steel

The evolution of dislocation loops in austenitic steels irradiated with Fe^(+)is investigated using cluster dynamics(CD)simulations by developing a CD model.The CD predictions are compared with experimental results in the literature.The number density and average diameter of the dislocation loops obtained from the CD simulations are in good agreement with the experimental data obtained from transmission electron microscopy(TEM)observations of Fe~+-irradiated Solution Annealed 304,Cold Worked 316,and HR3 austenitic steels in the literature.The CD simulation results demonstrate that the diffusion of in-cascade interstitial clusters plays a major role in the dislocation loop density and dislocation loop growth;in particular,for the HR3 austenitic steel,the CD model has verified the effect of temperature on the density and size of the dislocation loops.