As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient techniq...As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient technique to reduce the inductive noise.In this paper,the characteristics of on chip mutual inductance (as well as self) for coplanar,micro stripline and stripline structures are introduced first.Then base on the coplanar interconnect structures,the effective coupling K eff model and the RLC explicit noise model are proposed respectively.The results of experiments show that these two models both have high fidelity.展开更多
We develop an interconnect crosstalk estimation model on the assumption of linearity for CMOS device. First, we analyze the terminal response of RC model on the worst condition from theS field to the time domain. The ...We develop an interconnect crosstalk estimation model on the assumption of linearity for CMOS device. First, we analyze the terminal response of RC model on the worst condition from theS field to the time domain. The exact 3 order coefficients inS field are obtained due to the interconnect tree model. Based on this, a crosstalk peak estimation formula is presented. Unlike other crosstalk equations in the literature, this formula is only used coupled capacitance and grand capacitance as parameter. Experimental results show that, compared with the SPICE results, the estimation formulae are simple and accurate. So the model is expected to be used in such fields as layout-driven logic and high level synthesis, performance-driven floorplanning and interconnect planning.展开更多
Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources...Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .展开更多
文摘As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient technique to reduce the inductive noise.In this paper,the characteristics of on chip mutual inductance (as well as self) for coplanar,micro stripline and stripline structures are introduced first.Then base on the coplanar interconnect structures,the effective coupling K eff model and the RLC explicit noise model are proposed respectively.The results of experiments show that these two models both have high fidelity.
基金SupportedbytheNationalHighTechnologyResearchandDevelopmentProgramofChina (863Plan) (863 SOC Y 3 3 2 )
文摘We develop an interconnect crosstalk estimation model on the assumption of linearity for CMOS device. First, we analyze the terminal response of RC model on the worst condition from theS field to the time domain. The exact 3 order coefficients inS field are obtained due to the interconnect tree model. Based on this, a crosstalk peak estimation formula is presented. Unlike other crosstalk equations in the literature, this formula is only used coupled capacitance and grand capacitance as parameter. Experimental results show that, compared with the SPICE results, the estimation formulae are simple and accurate. So the model is expected to be used in such fields as layout-driven logic and high level synthesis, performance-driven floorplanning and interconnect planning.
基金This work was supported in part by the National Natural Science Foundation of China (Grant Nos. 69973027 and 60025101)by the National Fundamental Basic Research Program (973) (Grant No. G1999032903).
文摘Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .
