A 10 or 12 bit programmable successive approximation register(SAR) ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-do...A 10 or 12 bit programmable successive approximation register(SAR) ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-domain comparator are presented.The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC.Prototyped in a 0.18-m,6M1P CMOS process,the ADC,at 12 bit,100 kS/s,achieves a Nyquist signal-to-noise-plus-distortion ratio(SNDR) of 68 dB(11 ENOB),a spurious free dynamic range(SFDR) of 77.48 dB,while dissipating 558 W from a 1.8-V supply.Its differential nonlinearity(DNL) and integral nonlinearity(INL) are 0.2/-0.74 LSB and C1.27/-0.97 LSB,respectively.展开更多
基金Project supported by the PhD Programs Foundation of the Ministry of Education of China (No.20111011315)the National Science and Technology Important Project of China (No.2010ZX03006-003-01)
文摘A 10 or 12 bit programmable successive approximation register(SAR) ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-domain comparator are presented.The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC.Prototyped in a 0.18-m,6M1P CMOS process,the ADC,at 12 bit,100 kS/s,achieves a Nyquist signal-to-noise-plus-distortion ratio(SNDR) of 68 dB(11 ENOB),a spurious free dynamic range(SFDR) of 77.48 dB,while dissipating 558 W from a 1.8-V supply.Its differential nonlinearity(DNL) and integral nonlinearity(INL) are 0.2/-0.74 LSB and C1.27/-0.97 LSB,respectively.