A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.

A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS

With the explosive development of artificial intelligence(AI),machine learning(ML),and high-performance comput-ing(HPC),the ever-growing data movement is asking for high density interconnects with higher bandwidth(BW),lower power and lower latency[1−3].The optical I/O leverages silicon photonic(SiPh)technology to enable high-density large-scale integrated photonics.

A 24−30 GHz 8-element dual-polarized 5G FR2 phased-array transceiver IC with 20.8-dBm TX OP1dB and 4.1-dB RX NF in 65-nm CMOS

This article presents an 8-element dual-polarized phased-array transceiver(TRX)front-end IC for millimeter-wave(mm-Wave)5G new radio(NR).Power enhancement technologies for power amplifiers(PA)in mm-Wave 5G phased-array TRX are discussed.A four-stage wideband high-power class-AB PA with distributed-active-transformer(DAT)power combining and multi-stage second-harmonic traps is proposed,ensuring the mitigated amplitude-to-phase(AM-PM)distortions across wide carrier frequencies without degrading transmitting(TX)power,gain and efficiency.TX and receiving(RX)switching is achieved by a matching network co-designed on-chip T/R switch.In each TRX element,6-bit 360°phase shifting and 6-bit 31.5-dB gain tuning are respectively achieved by the digital-controlled vector-modulated phase shifter(VMPS)and differential attenuator(ATT).Fabricated in 65-nm bulk complementary metal oxide semiconductor(CMOS),the proposed TRX demonstrates the measured peak TX/RX gains of 25.5/21.3 dB,covering the 24−29.5 GHz band.The measured peak TX OP1dB and power-added efficiency(PAE)are 20.8 dBm and 21.1%,respectively.The measured minimum RX NF is 4.1 dB.The TRX achieves an output power of 11.0−12.4 dBm and error vector magnitude(EVM)of 5%with 400-MHz 5G NR FR2 OFDM 64-QAM signals across 24−29.5 GHz,covering 3GPP 5G NR FR2 operating bands of n257,n258,and n261.

Joint Transceiver Designs for Full-Duplex MIMO SWIPT Systems Based on MSE Criterion

For the simultaneous wireless information and power transfer(SWIPT), the full-duplex MIMO system can achieve simultaneous transmission of information and energy more efficiently than the half-duplex. Based on the mean-square-error(MSE) criterion, the optimization problem of joint transceiver design with transmitting power constraint and energy harvesting constraint is formulated. Next, by semidefinite relaxation(SDR) and randomization method, the SDRbased scheme is proposed. In order to reduce the complexity, the closed-form scheme is presented with some simplified measures. Robust beamforming is then studied considering the practical condition. The simulation results such as MSE versus signal-noise-ratio(SNR), MSE versus the iteration number, well prove the performance of the proposed schemes for the system model.

A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology

A 40 Gb/s full serializer and deserializer (SerDes) transceiver with controller and physical layer (PHY) is presented.The controller mainly contains protocol transmission, forward error correction and user layer build-in self-test (BIST).The physical coding sub-layer (PCS) provides the functions of 64/66 encoder/decoder, PHY BIST, and polarity control.In the physical medium attachment (PMA), both transmitter (TX) and receiver (RX) adopt quarter-rate architecture to relax the timing constraint and reduce power dissipation.The receiver utilizes the phase interpolator (PI) based clock and data recovery (CDR) with bang-bang phase detector (BBPD) to extract the synchronic clock for retiming and de-multiplexing.The multiple-MUX based 4-tap FFE and a two-stage cascade CTLE are employed to mitigate the inter-symbol interference (ISI).In addition, a proposed 4∶1 MUX is used to improve the output jitter performance and reduce the power consumption.Fabricated in a 65 nm CMOS technology, the full transceiver consumes 890 mW at 40 Gb/s and occupies 12 mm 2 .The measurement results show that this transceiver can achieve bit error rate (BER)< 10 -12 after a 15.3 dB loss channel at 20 GHz.

Mathematical Formulations of Signal Propagation in Ultra-Wideband Transceiver Systems under a UWB Channel Environment with an Extension of Frequency Offset Correction

This paper analyzes mathematically the crucial aspects of signal processing in a Multi-Band (MB) Orthogonal Frequency Division Multiplexing (OFDM) based system considering Ultra-Wideband (UWB) channel environment. In the process of analysis, it emphasizes the significant features of UWB receiver design in comparison with ‘conventional’ narrow-band system. The analysis shows that the high dispersive nature of a frequency selective UWB channel effects the design of different signal processing blocks like pre-select filter, low noise amplifier (LNA) and analog-to-digital (A/D) converter in the receiver front end. The characteristic functions of each of these stages are now dominated by the channel characteristics and it needs to be modified accordingly. This analysis is extended further with the study of frequency offset error and its correction. The unbiased Cramer Rao Lower Bound (CRLB) of estimation error is calculated and supported by computer simulation. The performance of an MB-OFDM system with frequency offset correction in terms of Bit-Error-Rate (BER) is also reported.

Decoupled estimation of frequency-dependent IQI and channel for OFDM systems with direct-conversion transceivers

The in-phase and quadrature-phase imbalance (IQI) is one of the major radio frequency impairments existing in orthogonal frequency division multiplexing (OFDM) systems with direct-conversion transceivers. During the transmission of the communication signal, the impact of IQI is coupled with channel impulse responses (CIR), which makes the traditional channel estimation schemes ineffective. A decoupled estimation scheme is proposed to separately estimate the frequency-dependent IQI and wireless channel. Firstly, the generalized channel model is built to separate the parameters of IQI and wireless channel. Then an iterative estimation scheme of frequency-dependent IQI is designed at the initial stage of communication. Finally, based on the estimation result of IQI, the least square algorithm is utilized to estimate the channel-related parameters at each time of channel variation. Compared with the joint estimation schemes of IQI and channel, the proposed decoupled estimation scheme requires much lower training overhead at each time of channel variation. Simulation results demonstrate the good estimation performance of the proposed scheme.

Silicon photonic transceivers for application in data centers

Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoelectronics transceivers in DCs,as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process.We also summarize the research on the main components in silicon photonic transceivers.In particular,quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts.Some of the solutions for highspeed optical interconnection in DCs are then discussed.Among them,wavelength division multiplexing and four-level pulseamplitude modulation have been widely studied and applied.At present,the application of coherent optical communication technology has moved from the backbone network,to the metro network,and then to DCs.

Design of 60GHz RF Transceiver in CMOS:Challenges and Recent Advances

With more than 40 years Moore scaling, the speed of CMOS transistors is around 100 GHz. Such fact makes it possible to realize mm-wave circuits in CMOS. However, with the target of achieving broadband and power-efficient operation, 60 GHz CMOS RF transceiver faces severe challenges. After reviewing the technology issues, regarding the 60 GHz applications, this paper discusses design challenges both from the system and the building block levels, and also presents some simulated or measured circuits results.

Precise Transceiver-Free Localization in Complex Indoor Environment

Transceiver-free object localization can localize target through using Radio Frequency(RF) technologies without carrying any device, which attracts many researchers' attentions. Most traditional technologies usually first deploy a number of reference nodes which are able to communicate with each other, then select only some wireless links, whose signals are affected the most by the transceiver-free target, to estimate the target position. However, such traditional technologies adopt an ideal model for the target, the other link information and environment interference behavior are not considered comprehensively. In order to overcome this drawback, we propose a method which is able to precisely estimate the transceiver-free target position. It not only can leverage more link information, but also take environmental interference into account. Two algorithms are proposed in our system, one is Best K-Nearest Neighbor(KNN) algorithm, the other is Support Vector Regression(SVR) algorithm. Our experiments are based on Telos B sensor nodes and performed in different complex lab areas which have many different furniture and equipment. The experiment results show that the average localization error is round 1.1m. Compared with traditional methods, the localization accuracy is increased nearly two times.

Low Power Single-Chip RF Transceiver for Human Body Communication

Human body communication is proposed as a promising body proximal communication technology for body sensor networks.To achieve low power and small volume in the sensor nodes,a Radio Frequency (RF) application-specific integrated circuit transceiver for Human Body Communication (HBC) is presented and the characteristics of HBC are investigated.A high data rate On-Off Keying (OOK)/Frequency-Shift Keying (FSK) modulation protocol and an OOK/FSK demodulator circuit are introduced in this paper,with a data-rate-to-carrier-frequency ratio up to 70%.A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path.In addition,a low power automatic-gain-control system is realized using a novel architecture,thereby rendering the peak detector circuit and loop filter unnecessary.Finally,the complete chip is fabricated.Simulation results suggest receiver sensitivity to be-75 dBm.The transceiver shows an overall power consumption of 3.2 mW when data rate is 5 Mbps,delivering a P1 dB output power of-30 dBm.

Microsphere femtosecond laser sub-50 nm structuring in far field via non-linear absorption

Creation of arbitrary features with high resolution is critically important in the fabrication of nano-optoelectronic devices.Here,sub-50 nm surface structuring is achieved directly on Sb2S3 thin films via microsphere femtosecond laser irradi-ation in far field.By varying laser fluence and scanning speed,nano-feature sizes can be flexibly tuned.Such small patterns are attributed to the co-effect of microsphere focusing,two-photons absorption,top threshold effect,and high-repetition-rate femtosecond laser-induced incubation effect.The minimum feature size can be reduced down to~30 nm(λ/26)by manipulating film thickness.The fitting analysis between the ablation width and depth predicts that the feature size can be down to~15 nm at the film thickness of~10 nm.A nano-grating is fabricated,which demonstrates desirable beam diffraction performance.This nano-scale resolution would be highly attractive for next-generation laser nano-lithography in far field and in ambient air.

Choice of optimal crystal-orientation for terahertz transceiver with zincblende crystal

This paper presents a set of equations describing the terahertz generation and electro-optic detection based on optical rectification in zincblende crystals. The dependence of terahertz emission efficiency on the polarization of incident beam and crystal-orientation is discussed. For the experimental setup with a transceiver which transmits and detects terahertz radiation in the same crystal, we have demonstrated the optimal combination of both parameters above to optimize the working efficiency. Equations supplied in this paper are valid for zincblende crystals with arbitrary crystal- orientation and every possible polarization of an incident beam, which are of great significance for the optimization of a system.

Transceiver Optimization for Multi-Antenna Device-to-Device Communications

It has been shown that the deployment of device-to-device(D2D) communication in cellular systems can provide better support for local services. However, improper design of the hybrid system may cause severe interference between cellular and D2D links. In this paper, we consider transceiver design for the system employing multiple antennas to mitigate the interference. The precoder and decoder matrices are optimized in terms of sum mean squared error(MSE) and capacity, respectively. For the MSE minimization problem, we present an alternative transceiver optimization algorithm. While for the non-convex capacity maximization problem, we decompose the primal problem into a sequence of standard convex quadratic programs for efficient optimization. The evaluation of our proposed algorithms for performance enhancement of the entire D2D integrated cellular system is carried out through simulations.

Design of an adaptive precoding/STBC baseband transceiver on a reconfigurable architecture

Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.

A Single-Chip UHF RFID Reader Transceiver IC

A single-chip UHF RFID reader transceiver IC has been implemented in 0.18 μm SiGe BiCMOS technology. The chip includes all transceiver blocks as RX/TX RF front-end, RX/TX analog baseband, frequency synthesizer and I2C with fully-compliant China 800/900 MHz RFID draft, ISO/IEC 18000-6C protocol and ETSI 302 208-1 local regulation. The normal mode receiver in the presence of -3 dBm self-jammer achieves -75 dBm 1% PER sensitivity. The linear class-A PA integrated in transmitter has 25 dBm OP1 dB output power for CW. The fully-integrated fractional-N fre-quency synthesizer is designed based on MASH 1-1-1 sigma-delta modulator and 1.8 GHz fundamental frequency LC-VCO for lower in-band and out-of-band phase noise. The measured phase noise is up to -106 dBc/Hz@200 kHz and -131 dBc/Hz@1 MHz offset from center frequency and the integrated RMS jitter from 10 kHz to 10 MHz is less than 1.6 pS. The chip dissipates 330 mA from 3.3 V power supply when transmitting 22.4 dBm CW signal and the PAE of linear PA is up to 26%. The chip die area is 16.8 mm2.

Ultra-Low Power 1 Volt Small Size 2.4 GHz CMOS RF Transceiver Design for Wireless Sensor Node

Ultra-low power transceiver design is proposed for wireless sensor node used in the wireless sensor network（WSN）.Typically,each sensor node contains a transceiver so it is required that both hardware and software designs of WSN node must take care of energy consumption during all modes of operation including active/sleep modes so that the operational life of each node can be increased in order to increase the lifetime of network.The current declared size of the wireless sensor node is of millimeter order,excluding the power source and crystal oscillator.We have proposed a new 2.4 GHz transceiver that has five blocks namely XO,PLL,PA,LNA and IF.The proposed transceiver incorporates less number of low-drop outs（LDOs）regulators.The size of the transceiver is reduced by decreasing the area of beneficiary components up to 0.41 mm;of core area in such a way that some functions are optimally distributed among other components.The proposed design is smaller in size and consumes less power,<1 mW,compared to other transceivers.The operating voltage has also been reduced to 1 V.This transceiver is most efficient and will be fruitful for the wireless networks as it has been designed by considering modern requirements.

A compact transmit/receive switch for 2.4 GHz reader-less active RFID tag transceiver

Radio frequency identification(RFID) is a ubiquitous identification technology nowadays. An on-chip high-performance transmit/receive(T/R) switch is designed and simulated in 0.13-μm CMOS technology for reader-less RFID tag. The switch utilizes only the transistor width and length(W/L) optimization, proper gate bias resistor and resistive body floating technique and therefore,exhibits 1 d B insertion loss, 31.5 d B isolation and 29.2 d Bm 1-d B compression point(P1d B). Moreover, the switch dissipates only786.7 n W power for 1.8/0 V control voltages and is capable of switching in 794 fs. Above all, as there is no inductor or capacitor used in the circuit, the size of the switch is 0.00208 mm2 only. This switch will be appropriate for reader-less RFID tag transceiver front-end as well as other wireless transceivers operated at 2.4 GHz band.

Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers

The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.

Analysis and Design of an Obstacle Detection Radar Transceiver for ISM Band

Authors designed an obstacle radar transceiver for ISM band. This work is focused on rectangular microstrip transceiver integrated with innovative metamaterial structure at a height of 3.276 mm from the ground plane. Two rectangular microstrip transceiver is designed for transmitting and receiving purpose. This work is mainly focused on increasing the potential parameters of rectangular microstrip transceiver. RMT along with the proposed innovative metamaterial structure is designed to resonate at 2.259 GHz. Simulation results showed that the impedance bandwidth of the RMT is improved by 575%, return loss is reduced by 391% and efficiency is improved by 28% by incorporating the proposed innovative metamaterial structure. For verifying that the proposed innovative metamaterial structure possesses negative values of Permeability and Permittivity within the operating frequency range, Nicolson-Ross-Weir method (NRW) has been employed. An op-amp and comparator is used to compare the return loss of transmitting and receiving RMT. An indicator is used to indicate difference of return loss and power of transmitting and receiving rectangular microstrip transceiver. For all simulation purpose, computer simulation technology-microwave studio (CST-MWS) software has been used.