An Improved Proportionate Normalized Least Mean Square Algorithm for Sparse Impulse Response Identification

In this paper after analyzing the adaptation process of the proportionate normalized least mean square(PNLMS) algorithm, a statistical model is obtained to describe the convergence process of each adaptive filter coefcient. Inspired by this result, a modified PNLMS algorithm based on precise magnitude estimate is proposed. The simulation results indicate that in contrast to the traditional PNLMS algorithm, the proposed algorithm achieves faster convergence speed in the initial convergence state and lower misalignment in the stead stage with much less computational complexity.

Chip Layout for Adaptive Line Enhancer Design using Adaptive Filtering Algorithms and Metrics Computation for Auscultation Signal Separation

Currently,the growth of micro and nano(very large scale integration-ultra large-scale integration)electronics technology has greatly impacted biomedical signal processing devices.These high-speed micro and nano technology devices are very reliable despite their capacity to operate at tremendous speed,and can be designed to consume less power in minimum response time,which is particularly useful in biomedical products.The rapid technological scaling of the metal-oxide-semi-conductor(MOS)devices aids in mapping multiple applications for a specific purpose on a single chip which motivates us to design a sophisticated,small and reliable application specific integrated circuit(ASIC)chip for future real time medical signal separation and processing(digital stetho-scopes and digital microelectromechanical systems(MEMS)microphone).In this paper,ASIC level implementation of the adaptive line enhancer design using adaptive filtering algorithms(least mean square(LMS)and normalized least mean square(NLMS))integrated design is used to separate the real-time auscultation sound signals effectively.Adaptive line enhancer(ALE)design is imple-mented in Verilog hardware description language(HDL)language to obtain both the network and adaptive algorithm in cadence Taiwan Semiconductor Manufacturing Company(TSMC)90 nm standard cell library environment for ASIC level implementation.Native compiled simulator(NC)sim and RC lab were used for functional verification and design constraints and the physical design is implemented in Encounter to obtain the Geometric Data Stream(GDS II).In this architecture,the area occupied is 0.08 mm,the total power consumed is 5.05 mW and the computation time of the proposed system is 0.82μs for LMS design and the area occupied is 0.14 mm,the total power consumed is 4.54 mW and the computation time of the proposed system is 0.03μs for NLMS design that will pave a better way in future electronic stethoscope design.