A novel non-volatile memory storage system for I/O-intensive applications

The emerging memory technologies, such as phase change memory （PCM）, provide chances for high- performance storage of I/O-intensive applications. However, traditional software stack and hardware architecture need to be optimized to enhance I/O efficiency. In addition, narrowing the distance between computation and storage reduces the number of I/O requests and has become a popular research direction. This paper presents a novel PCM- based storage system. It consists of the in-storage processing enabled file system （ISPFS） and the configurable parallel computation fabric in storage, which is called an in-storage processing （ISP） engine. On one hand, ISPFS takes full advantage of non-volatile memory （NVM）＇s characteristics, and reduces software overhead and data copies to provide low-latency high-performance random access. On the other hand, ISPFS passes ISP instructions through a command file and invokes the ISP engine to deal with I/O-intensive tasks. Extensive experiments are performed on the prototype system. The results indicate that ISPFS achieves 2 to 10 times throughput compared to EXT4. Our ISP solution also reduces the number of I/O requests by 97% and is 19 times more efficient than software implementation for I/O-intensive applications.

A Low-Power,Single-Poly,Non-Volatile Memory for Passive RFID Tags

Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.

Fabrication and integration of photonic devices for phase-change memory and neuromorphic computing

In the past decade,there has been tremendous progress in integrating chalcogenide phase-change materials(PCMs)on the silicon photonic platform for non-volatile memory to neuromorphic in-memory computing applications.In particular,these non von Neumann computational elements and systems benefit from mass manufacturing of silicon photonic integrated circuits(PICs)on 8-inch wafers using a 130 nm complementary metal-oxide semiconductor line.Chip manufacturing based on deep-ultraviolet lithography and electron-beam lithography enables rapid prototyping of PICs,which can be integrated with high-quality PCMs based on the wafer-scale sputtering technique as a back-end-of-line process.In this article,we present an overview of recent advances in waveguide integrated PCM memory cells,functional devices,and neuromorphic systems,with an emphasis on fabrication and integration processes to attain state-of-the-art device performance.After a short overview of PCM based photonic devices,we discuss the materials properties of the functional layer as well as the progress on the light guiding layer,namely,the silicon and germanium waveguide platforms.Next,we discuss the cleanroom fabrication flow of waveguide devices integrated with thin films and nanowires,silicon waveguides and plasmonic microheaters for the electrothermal switching of PCMs and mixed-mode operation.Finally,the fabrication of photonic and photonic–electronic neuromorphic computing systems is reviewed.These systems consist of arrays of PCM memory elements for associative learning,matrix-vector multiplication,and pattern recognition.With large-scale integration,the neuromorphic photonic computing paradigm holds the promise to outperform digital electronic accelerators by taking the advantages of ultra-high bandwidth,high speed,and energy-efficient operation in running machine learning algorithms.

Overview of one transistor type of hybrid organic ferroelectric non-volatile memory

Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent years.This emerging type of memory devices can lead to a new instrument system as a potential alternative to previous non-volatile memory building blocks in future processing units because of their numerous merits such as cost-effective process,simple structure and freedom in substrate choices.This bi-stable non-volatile memory device of information storage has been investigated using several organic or inorganic semiconductors with organic ferroelectric polymer materials.Recent progresses in this ferroelectric memory field,hybrid system have attracted a lot of attention due to their excellent device performance in comparison with that of all organic systems.In this paper,a general review of this type of ferroelectric non-volatile memory is provided,which include the device structure,organic ferroelectric materials,electrical characteristics and working principles.We also present some snapshots of our previous study on hybrid ferroelectric memories including our recent work based on zinc oxide nanowire channels.

Formation of high density TiN nanocrystals and its application in non-volatile memories

Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution of TiN-NCs can be controlled by annealing temperature. The formation of well separated crystalline TiN nano-dots with an average size of 5 nm is confirmed by transmission electron microscopy and x-ray diffraction, x-ray photoelectron spectroscopy confirms the existence of a transition layer of TiNxOy/SiON oxide between TiN-NC and SiO2, which reduces the barrier height of tunnel oxide and thereby enhances programming/erasing speed. The memory device shows a memory window of 2.5V and an endurance cycle throughout 10^5. Its charging mechanism, which is interpreted from the analysis of programming speed （dVth/dt） and the gate leakage versus voltage characteristics （Ig vs Vg）, has been explained by direct tunnelling for tunnel oxide and Fowler Nordheim tunnelling for control oxide at programming voltages lower than 9V, and by Fowler-Nordheim tunnelling for both the oxides at programming voltages higher than 9V.

Molecular dynamics simulations on the wet/dry self-latching and electric fields triggered wet/dry transitions between nanosheets:A non-volatile memory nanostructure

We design a nanostructure composing of two nanoscale graphene sheets parallelly immersed in water.Using molecular dynamics simulations,we demonstrate that the wet/dry state between the graphene sheets can be self-latched;moreover,the wet→dry/dry→wet transition takes place when applying an external electric field perpendicular/parallel to the graphene sheets(E;/E;).This structure works like a flash memory device(a non-volatile memory):the stored information(wet and dry states)of the system can be kept spontaneously,and can also be rewritten by external electric fields.On the one hand,when the distance between the two nanosheets is close to a certain distance,the free energy barriers for the transitions dry→wet and wet→dry can be quite large.As a result,the wet and dry states are self-latched.On the other hand,an E;and an E;will respectively increase and decrease the free energy of the water located in-between the two nanosheets.Consequently,the wet→dry and dry→wet transitions are observed.Our results may be useful for designing novel information memory devices.

An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies(Invited paper)

Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.

Design of an Electrically Written and Optically Read Non-volatile Memory Device Employing BiFeO3/Au Heterostructures with Strong Absorption Resonance

Exploiting new concepts for dense, fast, and nonvolatile random access memory with reduced energy consump- tion is a significant issue for information technology. Here we design an ＇electrically written and optically read＇ information storage device employing BiFeO3/A u heterostruetures with strong absorption resonance. The electro- optic effect is the basis for the device design, which arises from the strong absorption resonance in BiFeO3/Au heterostructures and the electrically tunable significant birefringence of the BiFeO3 film. We first construct a sim- ulation calculation of the BiFeO3/Au structure spectrum and identify absorption resonance and electro-optical modulation characteristics. Following a micro scale partition, the surface reflected light intensity of different polarization units is calculated. The results depend on electric polarization states of the BiFeO3 film, thus BiFeO3/Au heterostructures can essentially be designed as a type of electrically written and optically read infor- mation storage device by utilizing the scanning near-field optical microscopy technology based on the conductive silicon cantilever tip with nanofabricated aperture. This work will shed light on information storage technology.

Approximate Similarity-Aware Compression for Non-Volatile Main Memory

Image bitmaps,i.e.,data containing pixels and visual perception,have been widely used in emerging applica-tions for pixel operations while consuming lots of memory space and energy.Compared with legacy DRAM(dynamic ran-dom access memory),non-volatile memories(NVMs)are suitable for bitmap storage due to the salient features of high density and intrinsic durability.However,writing NVMs suffers from higher energy consumption and latency compared with read accesses.Existing precise or approximate compression schemes in NVM controllers show limited performance for bitmaps due to the irregular data patterns and variance in bitmaps.We observe the pixel-level similarity when writing bitmaps due to the analogous contents in adjacent pixels.By exploiting the pixel-level similarity,we propose SimCom,an approximate similarity-aware compression scheme in the NVM module controller,to efficiently compress data for each write access on-the-fly.The idea behind SimCom is to compress continuous similar words into the pairs of base words with runs.The storage costs for small runs are further mitigated by reusing the least significant bits of base words.SimCom adaptively selects an appropriate compression mode for various bitmap formats,thus achieving an efficient trade-off be-tween quality and memory performance.We implement SimCom on GEM5/zsim with NVMain and evaluate the perfor-mance with real-world image/video workloads.Our results demonstrate the efficacy and efficiency of our SimCom with an efficient quality-performance trade-off.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

Role of Cannabinoid CB1 Receptor in Object Recognition Memory Impairment in Chronically Rapid Eye Movement Sleep-deprived Rats

Objective We aimed to investigate whether antagonism of the cannabinoid CB1 receptor(CB1R)could affect novel object recognition(NOR)memory in chronically rapid eye movement sleep-deprived(RSD)rats.Methods The animals were examined for recognition memory following a 7-day chronic partial RSD paradigm using the multiple platform technique.The CB1R antagonist rimonabant(1 or 3 mg/kg,i.p.)was administered either at one hour prior to the sample phase for acquisition,or immediately after the sample phase for consolidation,or at one hour before the test phase for retrieval of NOR memory.For the reconsolidation task,rimonabant was administered immediately after the second sample phase.Results The RSD episode impaired acquisition,consolidation,and retrieval,but it did not affect the reconsolidation of NOR memory.Rimonabant administration did not affect acquisition,consolidation,and reconsolidation;however,it attenuated impairment of the retrieval of NOR memory induced by chronic RSD.Conclusions These findings,along with our previous report,would seem to suggest that RSD may affect different phases of recognition memory based on its duration.Importantly,it seems that the CB1R may,at least in part,be involved in the adverse effects of chronic RSD on the retrieval,but not in the acquisition,consolidation,and reconsolidation,of NOR memory.

声音的“性灵”——探微迟子建小说中声音的“唤醒功能”

迟子建在长达四十年的小说创作中,从《北极村童话》到《碾压甲骨的车轮》,持续采用声音作为叙事的元素。迟子建以细腻的笔触捕捉自然界与人类世界的各种声音,勾勒出自然、民间与历史的面貌。这不仅有助于小说营构诗意氛围、意象与主题意蕴,而且包孕着作家对外在世界独特的感觉结构。声音承载个人、家族与民族的“记忆”,抵达读者内心的深处,引起读者的共鸣。

新加坡小说《昭南岛的故事》中的二战记忆书写

《昭南岛的故事》是当代新马抗战华文文学的代表作之一,是李过根据搜集的战争亲历者和幸存者关于二战的回忆记载,基于历史经验,并结合史实进行构思而成。小说通过对一众小人物所思所为所遇的文学叙事,揭示了战时新加坡本土民族主义的觉醒与帝国统治衰落的过往,再现了日据时期新加坡各个阶层面对日本占领和高压统治表现出的抵抗、合作与中立的芸芸众生相,尤其建构了检证大屠杀给新加坡人民带来的集体创伤。小说所形塑的新加坡华人社会关于二战的集体记忆承载着作者铭记过往,建构身份认同与纾解疗愈集体创伤的意旨,也体现了新加坡华文文学界“我不记录,谁记录”的家国责任与担当。

追寻与建构:陈舜臣推理小说中的记忆书写与身份认同

华裔日本作家陈舜臣以推理小说享誉日本当代文坛,并在推理小说中探寻异文化中的身份认同问题。本文借助文化记忆理论,通过分析陈舜臣的代表性推理小说,尝试解答记忆在边缘人身份建构中的重要作用:身体记忆再现了边缘人的身份焦虑;地点记忆为主体提供了追寻身份之根的路径;文化记忆则消解了身份危机意识,构建了多元混杂的主体文化身份。在探讨全球化与文化多元化的今天,陈舜臣的记忆书写成为华裔作家确认身份认同的有效方式,同时为日本华裔群体的身份建构指明了出路和方向。

Chalcogenide Ovonic Threshold Switching Selector

Today’s explosion of data urgently requires memory technologies capable of storing large volumes of data in shorter time frames,a feat unattain-able with Flash or DRAM.Intel Optane,commonly referred to as three-dimensional phase change memory,stands out as one of the most promising candidates.The Optane with cross-point architecture is constructed through layering a storage element and a selector known as the ovonic threshold switch(OTS).The OTS device,which employs chalcogenide film,has thereby gathered increased attention in recent years.In this paper,we begin by providing a brief introduction to the discovery process of the OTS phenomenon.Subsequently,we summarize the key elec-trical parameters of OTS devices and delve into recent explorations of OTS materials,which are categorized as Se-based,Te-based,and S-based material systems.Furthermore,we discuss various models for the OTS switching mechanism,including field-induced nucleation model,as well as several carrier injection models.Additionally,we review the progress and innovations in OTS mechanism research.Finally,we highlight the successful application of OTS devices in three-dimensional high-density memory and offer insights into their promising performance and extensive prospects in emerging applications,such as self-selecting memory and neuromorphic computing.

论二战后缅甸战争小说中的记忆书写与历史叙事

二战后不久,缅甸获得独立,长期的反殖民、反帝国主义和反法西斯抗争使缅甸文坛掀起了战争文学创作热潮,各类战争题材小说层出不穷。缅甸作家或叙述战争体验,描写战争创伤,或重拾历史记忆,探寻历史教训,以促使人们铭记战争历史,思考民族命运。二战后的缅甸战争小说通过讲述历史人物的战斗故事,强化缅甸人民的民族身份认同。这些小说展现了不同时期的社会变迁,反映了作家对战争的认知。

个体记忆的叙事伦理——以池莉的《你是一条河》《来来往往》为例

以池莉《烦恼人生》、刘震云《一地鸡毛》为代表的新写实小说,注重对个体情感体验和日常生活的描写,试图通过个体记忆来还原客观的生活现实。池莉的小说以个体琐碎庸常的生活为主要叙述内容,在人物命名、个体情感的叙事中体现着作者对个体与时代关系的反思。同时,对生活中“不屈不挠的活”的方式的描写,推崇着底层社会的蓬勃生命力。在池莉小说中对生活经验的理解与思考源于作家的个人经验,由此呈现的个体生存状态、个人与群体的关系,能够引起当下反思。

Novell网络性能优化方法的探讨

深入分析了形成 Ｎｏｖｅｌｌ网络系统瓶颈的主要因素， 探讨了改善网络通信性能的主要途径， 即利用实发式外壳加强； 优化文件服务器以提高网络性能的各项方法。

A Survey of Non-Volatile Main Memory File Systems

Non-volatile memories(NVMs)provide lower latency and higher bandwidth than block devices.Besides,NVMs are byte-addressable and provide persistence that can be used as memory-level storage devices(non-volatile main memory,NVMM).These features change storage hierarchy and allow CPU to access persistent data using load/store instructions.Thus,we can directly build a file system on NVMM.However,traditional file systems are designed based on slow block devices.They use a deep and complex software stack to optimize file system performance.This design results in software overhead being the dominant factor affecting NVMM file systems.Besides,scalability,crash consistency,data protection,and cross-media storage should be reconsidered in NVMM file systems.We survey existing work on optimizing NVMM file systems.First,we analyze the problems when directly using traditional file systems on NVMM,including heavy software overhead,limited scalability,inappropriate consistency guarantee techniques,etc.Second,we summarize the technique of 30 typical NVMM file systems and analyze their advantages and disadvantages.Finally,we provide a few suggestions for designing a high-performance NVMM file system based on real hardware Optane DC persistent memory module.Specifically,we suggest applying various techniques to reduce software overheads,improving the scalability of virtual file system(VFS),adopting highly-concurrent data structures(e.g.,lock and index),using memory protection keys(MPK)for data protection,and carefully designing data placement/migration for cross-media file system.