A Novel Offset-Cancellation Technique for Low Voltage CMOS Differential Amplifiers

Based on a physical understanding of nonlinearity and mismatch, a novel offset-cancellation technique for low voltage CMOS differential amplifiers is proposed. The technique transfers the offset voltage from the output to other parts of the differential amplifier and can greatly reduce the input-referred offset voltage without extra power consumption. A 1.8V CMOS differential amplifier is implemented in 0.18μm CMOS process using the proposed technique. The simulation results show that the technique could reduce the input-referred offset voltage of the amplifier by 40% with a 20% load transistor mismatch and a 10% input differential transistor mismatch. Moreover, the proposed technique consumes the least power and achieves the highest integration among various offset-cancellation techniques.

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA（RXPGA） provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA（TXPGA） covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA （I and Q path） under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC（DC offset cancellation） circuit shows 10 kHz of HPCF（high pass cutoff frequency） and the DCOC settling time is less than 0.45μs.

A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 ×0.419 mm^2.

Beam-based calibrations of the BPM offset at C-ADS Injector Ⅱ

Beam-based BPM offset calibration was carried out for Injector II at the C-ADS demonstration facility at the Institute of Modern Physics （IMP）, Chinese Academy of Science （CAS）. By using the steering coils integrated in the quadrupoles, the beam orbit can be effectively adjusted and BPM positions recorded at the Medium Energy Beam Transport of the Injector II Linac. The studies were done with a 2 mA, 2.1 MeV proton beam in pulsed mode. During the studies, the ＂null comparison method＂ was applied for the calibration. This method is less sensitive to errors compared with the traditional transmission matrix method. In addition, the quadrupole magnet＇s center can also be calibrated with this method.

A continuously and widely tunable analog baseband chain with digital-assisted calibration for multi-standard DBS applications

This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/√Hz.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.

A high linearity downconverter for digital broadcasting system

An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 m CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 m A under a supply of 1.2 V.