Single event effects evaluation on convolution neural network in Xilinx 28 nm system on chip

Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects(SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm systemon-chip(SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.

Single-event-effect propagation investigation on nanoscale system on chip by applying heavy-ion microbeam and event tree analysis

The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locations and cross sections,for instance,the arithmetic logic unit,register,D-cache,and peripheral,while irradi-ating the on-chip memory(OCM)region.Moreover,event tree analysis was executed based on the obtained microbeam irradiation results.This study quantitatively assesses the probabilities of SEE propagation from the OCM to other blocks in the SoC.

Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

Atmospheric neutron single event effects for multiple convolutional neural networks based on 28-nm and 16-nm SoC

The single event effects(SEEs)evaluations caused by atmospheric neutrons were conducted on three different convolutional neural network(CNN)models(Yolov3,MNIST,and ResNet50)in the atmospheric neutron irradiation spectrometer(ANIS)at the China Spallation Neutron Source(CSNS).The Yolov3 and MNIST models were implemented on the XILINX28-nm system-on-chip(So C).Meanwhile,the Yolov3 and ResNet50 models were deployed on the XILINX 16-nm Fin FET Ultra Scale+MPSoC.The atmospheric neutron SEEs on the tested CNN systems were comprehensively evaluated from six aspects,including chip type,network architecture,deployment methods,inference time,datasets,and the position of the anchor boxes.The various types of SEE soft errors,SEE cross-sections,and their distribution were analyzed to explore the radiation sensitivities and rules of 28-nm and 16-nm SoC.The current research can provide the technology support of radiation-resistant design of CNN system for developing and applying high-reliability,long-lifespan domestic artificial intelligence chips.

SIMULATION AND PERFORMANCE ANALYSIS OF NETWORK ON CHIP ARCHITECTURES

The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.

Establishment of organoid models based on a nested array chip for fast and reproducible drug testing in colorectal cancer therapy

The conventional microwell-based platform for construction of organoid models exhibits limitations in precision oncology applications because of low-speed growth and high variability. Here, we established organoid models on a nested array chip for fast and reproducible drug testing using 50% matrigel. First, we constructed mouse small intestinal and colonic organoid models. Compared with the conventional microwell-based platform, the mouse organoids on the chip showed accelerated growth and improved reproducibility due to the nested design of the chip. The design of the chip provides miniaturized and uniform shaping of the matrigel that allows the organoid to grow in a concentrated and controlled manner. Next, a patient-derived organoid(PDO) model from colorectal cancer tissues was successfully generated and characterized on the chip. Finally, the PDO models on the chip, from three patients, were implemented for high-throughput drug screening using nine treatment regimens. The drug sensitivity testing on the PDO models showed good quality control with a coefficient of variation under 10% and a Z’ factor of more than 0.7. More importantly, the drug responses on the chip recapitulate the heterogeneous response of individual patients, as well as showing a potential correlation with clinical outcomes. Therefore,the organoid model coupled with the nested array chip platform provides a fast and reproducible means for predicting drug responses to accelerate precise oncology.

A New Method for Optimizing Layout Parameter ofan Integrated On-Chip Inductor in CMOSRF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.

A PRIORITY-BASED POLLING SCHEDULING ALGORITHM FOR ARBITRATION POLICY IN NETWORK ON CHIP

A solution is imperatively expected to meet the efficient contention resolution schemes for managing simultaneous access requests to the communication resources on the Network on Chip (NoC). Based on the ideas of conflict-free transmission, priority-based service, and dynamic self-adaptation to loading, this paper presents a novel scheduling algorithm for Medium Access Control (MAC) in NoC with the researches of the communication structure features of 2D mesh. The algorithm gives priority to guarantee the Quality of Service (QoS) for local input port as well as dynamic adjustment of the performance of the other ports along with input load change. The theoretical model of this algorithm is established with Markov chain and probability generating function. Mathematical analysis is made on the mean queue length and the mean inquiry cyclic time of the system. Simulated experiments are conducted to test the accuracy of the model. It turns out that the findings from theoretical analysis correspond well with those from simulated experiments. Further more, the analytical findings of the system performance demonstrate that the algorithm enables effectively strengthen the fairness and stability of data transmissions in NoC.

Delay Optimized Architecture for On-Chip Communication

Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh （2DDgl-Mesh） for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 （a network simulator） and CINS1M （a component based interconnection simulator） under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.

Tire Pressure Monitoring System Using SoC and Low Power Design

This paper presents the tire pressure monitoring system (TPMS) by using the system on chip (SoC) mixed signals with the help of Bluetooth transmission and in advantage of low power consumption design. This is to monitor the variations in temperature and pressure of the vehicle’s tire, and the TPMS system is involved. It improves the driver’s safety by automatically detecting the tire pressure and temperature and then warning signal is sent to driver to take a measure, which prevents from accident. The proposed system of tire pressure monitoring system using SoC increases the speed of indication time to the driver by using mixed signals. The inflation of the tire can be avoided by preventing from high temperature and high pressure. Limitation of temperature and pressure in the previous system is also elongated i.e. temperature from 40℃ to 125℃ and pressure from 0 to 750 Kpa. Sensors, wireless communication (Bluetooth dongle) and SoC unit are used to design the low power TPMS. Quantitative results are taken and the analogy between temperature and pressure is also verified. The tested results proved by need of the practical system. Signal conditioning voltage and SoC unit is the trace for low power design TPMS. Finally, the performance of the system is tested and executed by using proteus software given as a real time application.

Design and simulation of a Torus topology for network on chip

Aiming at the applications of NOC （network on chip） technology in rising scale and complexity on chip systems, a Torus structure and corresponding route algorithm for NOC is proposed. This Torus structure improves traditional Torus topology and redefines the denotations of the routers. Through redefining the router denotations and changing the original router locations, the Torus structure for NOC application is reconstructed. On the basis of this structure, a dead-lock and live-lock free route algorithm is designed according to dimension increase. System C is used to implement this structure and the route algorithm is simulated. In the four different traffic patterns, average, hotspot 13%, hotspot 67% and transpose, the average delay and normalization throughput of this Torus structure are evaluated. Then, the performance of delay and throughput between this Torus and Mesh structure is compared. The results indicate that this Torus structure is more suitable for NOC applications.

Research on Network-on-chip Dynamic and Adaptive Algorithm and Choice Strategy

With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves （30% - 47 %） and （ 20% - 39%） in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.

An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.

Design of Efficient Router with Low Power and Low Latency for Network on Chip

The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

Signal and Power Integrity Challenges for High Density System-on-Package

As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself,as the case for system-on-package(SoP),has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining,let alone improving,reliability and performance.The fundamental signal,power,and thermal integrity issues are discussed in detail,along with published techniques from around the industry to mitigate these issues in SoP applications.

A scalable and low power VLIW DSP core for embedded system design

Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to execute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less number of functional units according to the intended application. Low power support was added by careful architectural design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations, especially for compute intensive applications such as wire-line and wireless communications, including infrastructure and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effectively reduce the power consumption, chip area and time to market the intended final product.

A Miniaturized System for Neural Signal Acquiring and Processing

To collect neural activity data from awake, behaving freely animals, we develop miniaturized implantable recording system by the modem chip：Programmable System on Chip （PSoC） and through chronic electrodes in the cortex. With PSoC family member CY8C29466,the system completed operational and instrument amplifiers, filters, timers, AD convertors, and serial communication, etc. The signal processing was dealt with virtual instrument technology. All of these factors can significantly affect the price and development cycle of the project. The result showed that the system was able to record and analyze neural extrocellular discharge generated by neurons continuously for a week or more. This is very useful for the interdisciplinary research of neuroscience and information engineering technique. The circuits and architecture of the devices can be adapted for neurobiology and research with other small animals.

Multiplication Model of EMCCD Based on Single Type of Carrier

The avalanche multiplication principle of electron multiplication CCD (EMCCD) was discussed on the basis of single type of carrier, and the multiplication model was built by using a classic piecewise ionization rate model and avalanche multiplication integral formula. Wolff's ionization rate model was selected according to the structure and the multiplication gate amplitude of the actual devices. Compared the theoretical result with the multiplication curve of the actual device, it was found that only enough fringing field strength and multiplication area length could lead to adequate signal charge multiplication. The relationship between the multiplication gate amplitude and the total gain of the cascaded boosting EMCCD can be conveniently determined by using this model.

Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for Homogeneous MPSoCs

Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

A new approach for accurate determination of particle sizes in microfluidic impedance cytometry

In microfluidic impedance cytometry,the change in impedance is recorded as an individual cell passes through a channel between electrodes deposited on its walls,and the particle size is inferred from the amplitude of the impedance signal using calibration.However,because the current density is nonuniform between electrodes of finite width,there could be an error in the particle size measurement because of uncertainty about the location of the particle in the channel cross section.Here,a correlation is developed relating the particle size to the signal amplitude and the velocity of the particle through the channel.The latter is inferred from the time interval between the two extrema in the impedance curve as the particle passes through a channel with cross-sectional dimensions of 50μm(width)×30μm(height)with two pairs of parallel facing electrodes.The change in impedance is predicted using 3D COMSOL finite-element simulations,and a theoretical correlation that is independent of particle size is formulated to correct the particle diameter for variations in the cross-sectional location.With this correlation,the standard deviation in the experimental data is reduced by a factor of two to close to the standard deviation reported in the manufacturer specifications.