Research on the coordinated utilization of land resource in the intergrated economic region of industry, farming and grazing-a case study of Baotou city in Inner Mongolia

Baotou City is an industrial city developed in the farming-grazing transitional zone in northern China. The development of industry, farming and grazing is very fast. It has become a typical intergrated economic region of industry, farming and grazing. Based on the analysis of utilization of land resources, this paper points out the main conflicts and problems on the utilization of land resources in the city, and puts forward a corresponding proposal.

On-Chip Micro Temperature Controllers Based on Freestanding Thermoelectric Nano Films for Low-Power Electronics

Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.

High-intensity spatial-mode steerable frequency up-converter toward on-chip integration

Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domains without disturbing their quantum properties,nonlinear frequency conversion,typically steered with the quadratic(χ2)process,should be considered.Furthermore,another degree of freedom in steering the spatial modes during theχ2 process,with unprecedent mode intensity is proposed here by modulating the lithium niobate(LN)waveguide-based inter-mode quasi-phasematching conditions with both temperature and wavelength parameters.Under high incident light intensities(25 and 27.8 dBm for the pump and the signal lights,respectively),mode conversion at the sum-frequency wavelength with sufficient high output power(−7–8 dBm)among the TM01,TM10,and TM00 modes is realized automatically with characterized broad temperature(ΔT≥8°C)and wavelength windows(Δλ≥1 nm),avoiding the previous efforts in carefully preparing the signal or pump modes.The results prove that high-intensity spatial modes can be prepared at arbitrary transparent wavelength of theχ2 media toward on-chip integration,which facilitates the development of chip-based communication and quantum information systems because spatial correlations can be applied to generate hyperentangled states and provide additional robustness in quantum error correction with the extended Hilbert space.

Monolithically Integrating a 180° Bent Waveguide into a III-Nitride Optoelectronic On-Chip System

GaN-based devices have developed significantly in recent years due to their promising applications and research potential.A major goal is to monolithically integrate various GaN-based components onto a single chip to create future optoelectronic systems with low power consumption.This miniaturized integration not only enhances multifunctional performance but also reduces material,processing,and packaging costs.In this study,we present an optoelectronic on-chip system fabricated using a top-down approach on a III-nitride-on-silicon wafer.The system includes a near-ultraviolet light source,a monitor,a 180°bent waveguide,an electro-absorption modulator,and a receiver,all integrated without the need for regrowth or post-growth doping.35 Mbit/s optical data communication is demonstrated through light propagation within the system,confirming its potential for compact GaN-based optoelectronic solutions.

基于空间句法的老旧社区公共空间更新策略

随着城市化进程的持续深化,老旧小区的公共空间更新已成为城市发展中亟待解决的重大议题。以兰州市极具代表性的兰通厂社区作为研究对象,基于空间句法的分析手段,通过实地勘察并获取其公共空间数据,构建社区道路轴线模型,运用Depthmap软件深入剖析社区公共空间的整合度、选择度和可理解度,揭示公共空间存在的问题并从全新的维度提出一系列更新策略建议,旨在优化老旧小区公共空间环境,提升社区居民生活品质。

Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique

On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.

Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor

Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.

intergral ((asinx+bcosx)/(csinx+dcosx))dx的一种简便算法及其推广

本文对给出了一种简便算法，并把它推广到形如的积分，其中f（x），g（x）满足f（x）＝αf（x）＋βg（x），g′（x）＝γf（x）＋λg（x），a、b、c、d、α、β、γ、λ均是实数．

On-chip readout plasmonic mid-IR gas sensor

Gas identification and concentration measurements are important for both understanding and monitoring a variety of phenomena from industrial processes to environmental change.Here a novel mid-IR plasmonic gas sensor with on-chip direct readout is proposed based on unity integration of narrowband spectral response,localized field enhancement and thermal detection.A systematic investigation consisting of both optical and thermal simulations for gas sensing is presented for the first time in three sensing modes including refractive index sensing,absorption sensing and spectroscopy,respectively.It is found that a detection limit less than 100 ppm for CO2 could be realized by a combination of surface plasmon resonance enhancement and metal-organic framework gas enrichment with an enhancement factor over 8000 in an ultracompact optical interaction length of only several microns.Moreover,on-chip spectroscopy is demonstrated with the compressive sensing algorithm via a narrowband plasmonic sensor array.An array of 80 such sensors with an average resonance linewidth of 10 nm reconstructs the CO2 molecular absorption spectrum with the estimated resolution of approximately 0.01 nm far beyond the state-of-the-art spectrometer.The novel device design and analytical method are expected to provide a promising technique for extensive applications of distributed or portable mid-IR gas sensor.

Design Aspects of CMOS Compatible On-Chip Antenna for Applications of Contact-Less Smart Card

Design aspects of CMOS compatible on-chip antenna for applications of contact-less smart card are discussed.An on-chip antenna model is established and a design method is demonstrated.Experimental results show that system-on-chip integrating power reception together with other electronic functions of smart card applications is feasible.In a 6×10 -4T magnetic field of 22.5MHz,an on-chip power of 1.225mW for a 10kΩ load is obtained using a 4mm2 on-chip antenna.

Development of series SQUID array with on-chip filter for TES detector

A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.

Design of an unbuffered switch for network on-chip

In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.

On-Chip Capillary Electrophoresis (Chip-CE) with Optical On-Chip Leaky-Waveguide-Based Detection

Capillary electrophoresis (CE) suffers from a relatively small sensitivity—at least in case of optical detection transversely to the capillary axis due to the small capillary inner diameters in the range of 50 - 100 μm. Different concepts like bubble, U-, or Z-cells have been used to tackle that problem already in the nineties of the last century. But the U- and Z-cells have typically been extra cells with larger inner channel diameters and no optimization for optical waveguiding and the bubble cell per se did not allow for optical waveguiding. In the case of on-chip capillary electrophoresis (chip-CE) a U-cell can be implemented quite easily on the chip. Here we show how leaky optical waveguiding can be employed to improve optical detection. Proper U-channel design and preparation by wet-chemical etching of the fused silica sub- and superstrate, making the U-channel bend a part of the optical input lens system, can help to achieve high coupling efficiency with loss coefficients around 2 dB and low waveguiding loss.

A Single Mode Hybrid Ⅲ-Ⅴ/Silicon On-Chip Laser Based on Flip-Chip Bonding Technology for Optical Interconnection

A single mode hybrid Ⅲ-Ⅴ/silicon on-chip laser based on the flip-chip bonding technology for on-chip optical interconnection is demonstrated. A single mode Fabry-Perot laser structure with micro-structures on an InP ridge waveguide is designed and fabricated on an InP/AIGaInAs multiple quantum well epitaxial layer structure wafer by using i-line lithography. Then, a silicon waveguide platform including a laser mounting stage is designed and fabricated on a silicon-on-insulator substrate. The single mode laser is flip-chip bonded on the laser mounting stage. The lasing light is butt-coupling to the silicon waveguide. The laser power output from a silicon waveguide is 1.3roW, and the threshold is 37mA at room temperature and continuous wave operation.

Area Analysis for On-chip Routers with Different Data-link Widths

Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.

《CHEINESE JOURNAL OF INTERGRATIVE MEDICINE》2009年征订启事

《CHINESEJOURNAL OF INTEGRATIVE MEDICINE》自2009年起改为双月刊(逢双月出版),大16开,80页,国内外公开发行,国内定价:25.00元/期,全年150.00元,全国各地邮局均可订阅,邮发代号:

多元主体协同共建现代产业学院的模式创设与推进路径

现代产业学院作为当前校企合作、产教融合及科教融汇的一种办学综合体,其生成与发展具有特殊的时代特征与价值意蕴。文章就现代产业学院概念内涵、多元功能、发展现状等问题作了分析梳理。分析了现实困境及共性个性问题;从模式创设、建立机构、共建专业、共育师资、课程建设、开发项目、文化培育七个方面阐释了建设内容和方法;提出了“1+1+N”组建模式、“三个提升”“1+1>2”“1+1+N>2+N”协同效应、“7+X”功能拓展等观点。

“海洋生物学”课程思政元素挖掘初探

“海洋生物学”是涉海高校本科生一门非常重要的专业基础课,在海洋科学、海洋环境科学等专业人才培养中具有重要作用。面对国家海洋生物分类专业人才需求和枯燥繁多的海洋生物分类知识,通过海洋生物分类科学思维方法的训练,在海洋生物学课程思政建设探索和实践过程中凝练出“六个一精神”思政元素。期待通过“海洋生物学”课程的“六个一精神”融入课程思政建设的总体布局,和其他思政元素一起,共同坚定大学生的理想信念,培养出建设海洋强国的高素质专业人才。