Structure and electrical properties of polysilicon films doped with ammonium tetraborate tetrahydrate

Here,p-type polysilicon films are fabricated by ex-situ doping method with ammonium tetraborate tetrahydrate(ATT)as the boron source,named ATT-pPoly.The effects of ATT on the properties of polysilicon films are comprehensively analyzed.The Raman spectra reveal that the ATT-pPoly film is composed of grain boundary and crystalline regions.The preferred orientation is the(111)direction.The grain size increases from 16−23 nm to 21−47 nm,by~70%on average.Comparing with other reported films,Hall measurements reveal that the ATT-pPoly film has a higher carrier concentration(>10^(20)cm^(−3))and higher carrier mobility(>30 cm2/(V·s)).The superior properties of the ATT-pPoly film are attributed to the heavy doping and improved grain size.Heavy doping property is proved by the mean sheet resistance(Rsheet,m)and distribution profile.The R_(sheet,m)decreases by more than 30%,and it can be further decreased by 90%if the annealing temperature or duration is increased.The boron concentration of ATT-pPoly film annealed at 950℃ for 45 min is~3×10^(20)cm^(−3),and the distribution is nearly the same,except near the surface.Besides,the standard deviation coefficient(σ)of Rsheet,m is less than 5.0%,which verifies the excellent uniformity of ATT-pPoly film.

On-Chip Micro Temperature Controllers Based on Freestanding Thermoelectric Nano Films for Low-Power Electronics

Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.

High-intensity spatial-mode steerable frequency up-converter toward on-chip integration

Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domains without disturbing their quantum properties,nonlinear frequency conversion,typically steered with the quadratic(χ2)process,should be considered.Furthermore,another degree of freedom in steering the spatial modes during theχ2 process,with unprecedent mode intensity is proposed here by modulating the lithium niobate(LN)waveguide-based inter-mode quasi-phasematching conditions with both temperature and wavelength parameters.Under high incident light intensities(25 and 27.8 dBm for the pump and the signal lights,respectively),mode conversion at the sum-frequency wavelength with sufficient high output power(−7–8 dBm)among the TM01,TM10,and TM00 modes is realized automatically with characterized broad temperature(ΔT≥8°C)and wavelength windows(Δλ≥1 nm),avoiding the previous efforts in carefully preparing the signal or pump modes.The results prove that high-intensity spatial modes can be prepared at arbitrary transparent wavelength of theχ2 media toward on-chip integration,which facilitates the development of chip-based communication and quantum information systems because spatial correlations can be applied to generate hyperentangled states and provide additional robustness in quantum error correction with the extended Hilbert space.

Monolithically Integrating a 180° Bent Waveguide into a III-Nitride Optoelectronic On-Chip System

GaN-based devices have developed significantly in recent years due to their promising applications and research potential.A major goal is to monolithically integrate various GaN-based components onto a single chip to create future optoelectronic systems with low power consumption.This miniaturized integration not only enhances multifunctional performance but also reduces material,processing,and packaging costs.In this study,we present an optoelectronic on-chip system fabricated using a top-down approach on a III-nitride-on-silicon wafer.The system includes a near-ultraviolet light source,a monitor,a 180°bent waveguide,an electro-absorption modulator,and a receiver,all integrated without the need for regrowth or post-growth doping.35 Mbit/s optical data communication is demonstrated through light propagation within the system,confirming its potential for compact GaN-based optoelectronic solutions.

Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique

On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.

Fabrication of n^+ Polysilicon Ohmic Contacts with a Heterojunction Structure to n-Type 4H-Silicon Carbide

Polysilicon ohmic contacts to n-type 4H-SiC have been fabricated. TLM （transfer length method） test patterns with polysilicon structure are formed on n-wells created by phosphorus ion （P^＋） implantation into a Si-faced p-type 4H-SiC epilayer. The polysilicon is deposited using low-pressure chemical vapor deposition （LPCVD） and doped by phosphorous ions implantation followed by diffusion to obtain a sheet resistance of 22Ω/□. The specific contact resistance pc of n^＋ polysilicon contact to n-type 4H-SiC as low as 3.82 × 10^-5Ω· cm^2 is achieved. The result for sheet resistance Rsh of the phosphorous ion implanted layers in SiC is about 4.9kΩ/□. The mechanisms for n^＋ polysilicon ohmic contact to n-type SiC are discussed.

Resistivity Instability in Polysilicon Resistors Under Metal Interco-nnects and Its Suppression by Compensating Ion Implantation

The resistivity instability of the boron-doped polysilicon resistors being a line resistance element of ICs is within the range of several kΩ's,especially when our running the underneath metal interconnects.Polysilicon resistors have been fabricated under various processing conditions as well as some electrical and crystallographic characteristics have been obtained.It is shown the resistivity instability mainly results from the variational carrier mobility.By analyzing the Seto's model,the barrier height and trapped charge density are observed reducing under the Al over layer.Therefore,the resistance instability is also caused by both the charge trapping/detrapping occurring at polysilicon grain boundaries and the resultant variation in the potential barrier height.The formation of high-stability polysilicon resistors in the range of several kΩ's has been decided by compensating the ion implantation,which makes the charge trapping/detrapping at the grain boundary less susceptible to the hydrogen annealing.

Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor

Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.

Polysilicon Over-Etching Time Control of Advanced CMOS Processing with Emission Microscopy

The emission microscopy （EMMI） test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure, named a poly-edge structure. From the values of the breakdown voltage （Vbd） of MOS capacitors （poly-edge structure） ,it was observed that,with for the initial polysilicon etching-time, almost all capacitors in one wafer failed under the initial failure model. With the increase of polysilicon over-etching time, the number of the initial failure capacitors decreased. Finally, no initial failure capacitors were observed after the polysilicon over-etching time was increased by 30s. The breakdown samples with the initial failure model and intrinsic failure model underwent EMMI tests. The EMMI test results show that the initial failure of capacitors with poly-edge structures was due to the bridging effect between the silicon substrate and the polysilicon gate caused by the residual polysilicon in the ditch between the shallow-trench isolation region and the active area, which will short the polysilicon gate with silicon substrate after the silicide process.

国产化叠层电容工艺的失效机理与可靠性研究

通过对国产运算放大器的一项失效分析研究,揭示了由于工艺变更引起的叠层MIS电容短路是导致器件失效的主要原因。在低电场条件下,电容表现正常,但在高电场条件下,由于Fowler Nordheim隧穿效应,热电子碰撞引发的缺陷积累最终导致了电容的短路失效。通过Sentaurus TCAD仿真分析,验证了界面掺杂原子浓度差异对氧化层生长速率的影响,并提出了相应的工艺改进建议,进而提升国产芯片的可靠性。

On-chip readout plasmonic mid-IR gas sensor

Gas identification and concentration measurements are important for both understanding and monitoring a variety of phenomena from industrial processes to environmental change.Here a novel mid-IR plasmonic gas sensor with on-chip direct readout is proposed based on unity integration of narrowband spectral response,localized field enhancement and thermal detection.A systematic investigation consisting of both optical and thermal simulations for gas sensing is presented for the first time in three sensing modes including refractive index sensing,absorption sensing and spectroscopy,respectively.It is found that a detection limit less than 100 ppm for CO2 could be realized by a combination of surface plasmon resonance enhancement and metal-organic framework gas enrichment with an enhancement factor over 8000 in an ultracompact optical interaction length of only several microns.Moreover,on-chip spectroscopy is demonstrated with the compressive sensing algorithm via a narrowband plasmonic sensor array.An array of 80 such sensors with an average resonance linewidth of 10 nm reconstructs the CO2 molecular absorption spectrum with the estimated resolution of approximately 0.01 nm far beyond the state-of-the-art spectrometer.The novel device design and analytical method are expected to provide a promising technique for extensive applications of distributed or portable mid-IR gas sensor.

Design Aspects of CMOS Compatible On-Chip Antenna for Applications of Contact-Less Smart Card

Design aspects of CMOS compatible on-chip antenna for applications of contact-less smart card are discussed.An on-chip antenna model is established and a design method is demonstrated.Experimental results show that system-on-chip integrating power reception together with other electronic functions of smart card applications is feasible.In a 6×10 -4T magnetic field of 22.5MHz,an on-chip power of 1.225mW for a 10kΩ load is obtained using a 4mm2 on-chip antenna.

MECHANICAL DEFLECTION OF POLYSILICON MICROCANTILEVER BEAMS USING NANOINDENTATION

The validity of a novel, direct and convenient method for micromechanical property measurements by beam bending using a nanoindenter is demonstrated. This method combines a very high load resolution with a nanometric precision in the determination of the microcantilever beam deflection. The method is described clearly. In the deflection of microbeams, the influence of the indenter tip pushing into the top of the microbeams and the curvature across its width must be considered. The measurements were made on single-layer, micro-thick, several kinds of width and length polysilicon beams that were fabricated using conventional integrated circuit (IC) fabrication techniques. The elastic of a polysilicon microcantilever beam will vary linearly with the force and the deformation is thought to be elastic. Furthermore, it suggests that Young modulus of the beam can be determined from the slope of this linear relation. From the load deflection data acquired during bending the mechanical properties of the thin films were determined. Measured Young modulus is 137 GPa with approximately a ±2.9%～±6.3% difference in Young modulus.

Numerical simulation of chemical vapor deposition reaction in polysilicon reduction furnace

Three-dimensional model of chemical vapor deposition reaction in polysilicon reduction furnace was established by considering mass, momentum and energy transfer simultaneously. Then, CFD software was used to simulate the flow, heat transfer and chemical reaction process in reduction furnace and to analyze the change law of deposition characteristic along with the H_2 mole fraction, silicon rod height and silicon rod diameter. The results show that with the increase of H_2 mole fraction, silicon growth rate increases firstly and then decreases. On the contrary, SiHCl_3 conversion rate and unit energy consumption decrease firstly and then increase. Silicon production rate increases constantly. The optimal H_2 mole fraction is 0.8-0.85. With the growth of silicon rod height, Si HCl3 conversion rate, silicon production rate and silicon growth rate increase, while unit energy consumption decreases. In terms of chemical reaction, the higher the silicon rod is, the better the performance is. In the view of the top-heavy situation, the actual silicon rod height is limited to be below 3 m. With the increase of silicon rod diameter, silicon growth rate decreases firstly and then increases. Besides, SiHCl_3 conversion rate and silicon production rate increase, while unit energy consumption first decreases sharply, then becomes steady. In practice, the bigger silicon rod diameter is more suitable. The optimal silicon rod diameter must be over 120 mm.

Development of series SQUID array with on-chip filter for TES detector

A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.

Organic field-effect transistor floating-gate memory using polysilicon as charge trapping layer

In this study,we present an organic field-effect transistor floating-gate memory using polysilicon(poly-Si)as a charge trapping layer.The memory device is fabricated on a N^+-Si/SiO2 substrate.Poly-Si,polymethylmethacrylate,and pentacene are used as a floating-gate layer,tunneling layer,and active layer,respectively.The device shows bidirectional storage characteristics under the action of programming/erasing(P/E)operation due to the supplied electrons and holes in the channel and the bidirectional charge trapping characteristic of the poly-Si floating-gate.The carrier mobility and switching current ratio(Ion/Ioff ratio)of the device with a tunneling layer thickness of 85 nm are 0.01 cm^2·V^-1·s^-1 and 102,respectively.A large memory window of 9.28 V can be obtained under a P/E voltage of±60 V.

The Antioxidation Properties of the In-situ Ceramic from Pyrolyzing Polysilicone Preceramic

A systematic research on the pyrolysis process of polymethysilicone (SAR-2) and the thermostability of the pyrolysis residue was made by the thermogravimetric analysis, DTA and infrared spectroscopy.The experimental results indicate that the pyrolysis residue of SAR-2 converted into the amorphous SiC_xO_(4-x) phase above 900 ℃,the residue at 1200 ℃ is the most thermostable and antioxidant.It is suitable to be used as polysilicone preceramic.

SIZE EFFECT ON THE BENDING AND TENSILE STRENGTH OF MICROMACHINED POLYSILICON FILMS FOR MEMS

The bending strength of microfabricated polysilicon beams was measured by beam bending using a nanoindenter. Also, the tensile strength of microfabricated polysilicon thin ?lms was measured by tensile testing with a new microtensile test device. It was found that the bending strength and tensile strength of polysilicon microstructures exerts size e?ect on the size of the specimens. In such cases, the size e?ect can be traced back to the ratio of surface area to volume as the governing parameter. A statistical analysis of the bending strength for various specimen sizes shows that the average bending strength of polysilicon microcantilever beams is 2.885 ± 0.408 GPa. The measured average value of Young’s modulus, 164 ± 1.2 GPa, falls within the theoretical bounds. The average fracture tensile strength is 1.36 GPa with a standard deviation of 0.14 GPa, and the Weibull modulus is 10.4 -11.7, respectively. The tensile testing of 40 specimens on failure results in a recommendation for design that the nominal strain be maintained below 0.0057.

MODEL AND MODELING OF LOW TEMPERATURE CURRENT GAIN OF POLYSILICON EMITTER BIPOLAR TRANSISTORS

A unified model of low temperature current gain of polysilicon emitter bipolar transistors based on effective recombination method is presented, incorporating band-gap narrowing, carrier freezing-out, tunneling of holes through polysilicon/silicon interface oxide layer and reduced mobility mechanism in polysilicon. The modeling results based on this model are in good agreement with experimental data.