A Thermal-Conscious Integrated Circuit Power Model and Its Impact on Dynamic Voltage Scaling Techniques

We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.

Fast Analysis of Power/Ground Networks via Circuit Reduction

This paper presents an efficient algorithm for reducing RLC power/ground network complexities by exploitation of the regularities in the power/ground networks. The new method first builds the equivalent models for many series RLC-current chains based on their Norton＇s form companion models in the original networks,and then the precondition conjugate gradient based iterative method is used to solve the reduced networks,which are symmetric positive definite. The solutions of the original networks are then back solved from those of the reduced networks.Experimental results show that the complexities of reduced networks are typically significantly smaller than those of the original circuits, which makes the new algorithm extremely fast. For instance, power/ground networks with more than one million branches can be solved in a few minutes on modern Sun workstations.

A New Type of Power Clock for DSCRL Adiabatic Circuit

An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,used in the DSCRL adiabatic circuit.Although the 4 phase power clock is simpler,the DSCRL adiabatic circuit still shows good performance and high efficiency of energy transfer and recovery.This conclusion has been proved by the result of the HSPICE simulation using the 0 6μm CMOS technology.

A Slice Analysis-Based Bayesian Inference Dynamic Power Model for CMOS Combinational Circuits

To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and internal node state, we find the deficiency of only using port information. Then, we define the gate level number computing method and the concept of slice, and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information. Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model, and maintain a 700 ＋ speedup compared with the existing gate-level power analysis technique.

Energy-efficient data transmission with non-ideal circuit power for downlink cellular networks

The downlink energy-efficient transmission schedule with non-ideal circuit power over Wreless networks involving a single transmitter and multiple receivers was investigated. According to the special structure of the problem, a novel algorithm called OOSCPMR （the optimal offine scheduling with non-ideal circuit power for multi-receivers） is proposed, and the optimal offine solutions to optimize the energy- efficient transmission policy are found. The packets to be transmitted can be divided into two types where one type of packet is determined to be transmitted using the enrgy- efficient tansmission time, and the other type of packet is determined by the ID moveright algorithm. Finally, an energy-efficient online schedule is developed based on te proposed OOSCPMR algoriAm. Simulation results show that the optima offline transmission schedule provides te lower bound performance for the online tansmission schedule. The proposed optimal offline and online policy is more energy efficient than the existing schemes tat assume ideal circuit power.

Energy Recovery Threshold Logic and Power Clock Generation Circuits

Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.

Low power consumption 4-channel variable optical attenuator array based on planar lightwave circuit technique

The power consumption of a variable optical attenuator（VOA） array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis. The simulation results showed that the power consumption reduces as the depth of the heat-insulating grooves is deeper, the up-cladding is thinner,the down-cladding is thicker, and the width of the cladding ridge is narrower. The materials component and thickness of the electrodes were also optimized to guarantee the driving voltage under 5 V. The power consumption was successfully reduced to as low as 155 mW at an attenuation of 30 dB in the experiment.

Investigation on Flow Accelerated Corrosion Mitigation for Secondary Circuit Piping of the Third Qinshan Nuclear Power Plant

Flow accelerated corrosion（FAC） is the main failure cause of the secondary circuit carbon steel piping in nuclear power plants.The piping failures caused by FAC have resulted in numerous unplanned outages and tragic fatalities.The existing researches focus on the main factors contributing to FAC,which include metallurgical factors,environmental factors and hydrodynamic factors. Some effective FAC management methods and programs with long term monitoring and inspection data analysis are recommended.But a comprehensive FAC management system should be developed in order to mitigate and manage FAC systematically.In this paper,the FAC influencing factors are analyzed in combination with the operating conditions of the secondary circuit piping in the Third Qinshan Nuclear Power Plant（TQNPP）,China（Third Qinshan Nuclear Power Company Limited,China）.A comprehensive FAC mitigation and management system is developed for TQNPP secondary circuit piping.The system is composed of five processes,viz.materials substitution,water chemical optimization,long-term monitor strategy for the susceptible piping,integrity evaluation of the local thinning defects,and repair or replacement.With the implementation of the five processes,the material of FAC sensitive pipe fittings are modified from carbon steel to stainless steel,N_2H_4 and NH_3 are finally selected as the water chemical regulator of secondary circuit,the secondary circuit pips are classified according to FAC susceptibility in order to conduct long term monitoring strategy,and an integrity evaluation flow for local thinning caused by FAC in carbon steel piping is developed.If the component with local thinning defects is not fit-for-service,corresponding repair or replacement should be conducted.The comprehensive FAC mitigation and management system with five interrelated processes would be a cost-effective method of increasing personnel safety,plant safety and availability.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

Simulation realization of skip cycle mode integrated control circuit in the switching power supply with low standby loss

This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27℃ and 90℃. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply （SMPS） works with low load or without load.

Power Prediction of VLSI Circuits Using Machine Learning

The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,heat research,and IR-drop research that results in extended running times.This unit focuses on the assessment of test strength.Because of the enormous number of successful designs for currentmodels and the unnecessary time required for every test,maximum energy ratings with all tests cannot be achieved.Nevertheless,test safety is important for producing trustworthy findings to avoid loss of output and harm to the chip.Generally,effective power assessment is only possible in a limited sample of pre-selected experiments.Thus,a key objective is to find the experiments that might give the worst situations again for testing power.It offers a machine-based circuit power estimation(MLCPE)system for the selection of exams.Two distinct techniques of predicting are utilized.Firstly,to find testings with power dissipation,it forecasts the behavior of testing.Secondly,the changemovement and energy data are linked to the semiconductor design,identifying small problem areas.Several types of algorithms are utilized.In particular,the methods compared.The findings show great accuracy and efficiency in forecasting.That enables such methods suitable for selecting the worst scenario.

Incidence Colorings of Powers of Circuits

The incidence chromatic number of G is the least number of colors such that G has an incidence coloring. It is proved that the incidence chromatic number of Cn^p, the p-th power of the circuit graph, is 2p ＋ 1 if and only if n = k（2p ＋ 1）, for other cases： its incidence chromatic number is at most 2p ＋ [r/k] ＋ 2, where n = k（p ＋ 1） ＋ r, k is a positive integer. This upper bound is tight for some cases.

Fault Diagnosis of Power Electronic Circuits Based on Adaptive Simulated Annealing Particle Swarm Optimization

In the field of energy conversion,the increasing attention on power electronic equipment is fault detection and diagnosis.A power electronic circuit is an essential part of a power electronic system.The state of its internal components affects the performance of the system.The stability and reliability of an energy system can be improved by studying the fault diagnosis of power electronic circuits.Therefore,an algorithm based on adaptive simulated annealing particle swarm optimization(ASAPSO)was used in the present study to optimize a backpropagation(BP)neural network employed for the online fault diagnosis of a power electronic circuit.We built a circuit simulation model in MATLAB to obtain its DC output voltage.Using Fourier analysis,we extracted fault features.These were normalized as training samples and input to an unoptimized BP neural network and BP neural networks optimized by particle swarm optimization(PSO)and the ASAPSO algorithm.The accuracy of fault diagnosis was compared for the three networks.The simulation results demonstrate that a BP neural network optimized with the ASAPSO algorithm has higher fault diagnosis accuracy,better reliability,and adaptability and can more effectively diagnose and locate faults in power electronic circuits.

Overview of Circuit Topologies for Inductive Pulsed Power Supplies

The pulsed power supply(PPS)is one important component in the electromagnetic launch system.The inductive PPSs have attracted researchers’attentions with the major advantages of high energy storage density(over the capacitive PPSs)as well as simple structure and easy control(over the rotating mechanical PPSs).As for the inductive PPSs,the circuit topology of the basic module will directly determine the comprehensive performance of the whole system.From the perspectives of working principles,strengths,weaknesses,and comprehensive performance,this paper presents a historical and technical review of the major circuit topologies for the inductive PPSs.

SYNCHRONOUS DERIVED CLOCK AND SYNTHESIS OF LOW POWER SEQUENTIAL CIRCUITS

Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.

Ultra-Low Power Pipeline Structure Exploiting Noncritical Stage with Circuit-Level Timing Speculation

With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.

Power Management Integrated Circuit with 90Plus Efficiency Used in AC/DC Converter

Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is proposed in this paper. The new topology can correspond to a 90 plus percent of power converting. So,a novel topology of an state of-art integrated circuit, which can be used as power management circuit, has been designed based on the above new topology. A simulator which is specific suitable for the power controller has been founded in this work and it has been used for the simulation of the novel architecture and the proposed integrated circuit.

A terahertz on-chip InP-based power combiner designed using coupled-grounded coplanar waveguide lines

This article presents the design and performance of a terahertz on-chip coupled-grounded coplanar waveguide(GCPW)power combiner using a 50μm-thick InP process.The proposed topology uses two coupled-GCPW lines at the end of the input port to substitute two quarter-wavelength GCPW lines,which is different from the conventional Wilkinson power combiner and can availably minimize the coverage area.According to the results obtained,for the frequency range of 210-250 GHz,the insertion losses for each two-way combiner and four-way combiner were lower than 1.05 dB and1.35 dB,respectively,and the in-band return losses were better than 11 dB.Moreover,the proposed on-chip GCPW-based combiners achieved a compromise in low-loss,broadband,and small-size,which can find wide applications in terahertz bands,such as power amplifiers and signal distribution networks.

A novel design of power management integrated circuit with 90 plus efficiency used in AC/DC converter

Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is proposed in this paper. The new topology can correspond to a 90 plus percent of power converting. So,a novel topology of an state of art integrated circuit, which can be used as power management circuit, has been designed based on the above new topology. A simulator which is specifically suitable for the power controller has been founded in this work and it has been used for the simulation of the novel architecture and the proposed integrated circuit.

Study on High-power LED Heat Dissipation Based on Printed Circuit Board

In order to study the role of printed circuit board(PCB)in high-power LED heat dissipation,a simple model of high-power LED lamp was designed.According to this lamp model,some thermal performances such as thermal resistances of four types of PCB and the changes of LED junction temperature were tested under three different working currents.The obtained results indicate that LED junction temperature can not be lowered significantly with the decreasing thermal resistance of PCB.However,PCB with low thermal resistance can be matched with smaller volume heat sink,so it is hopeful to reduce the size,weight and cost of LED lamp.