This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM （Partially Depleted Silicon- On-Insulator Static Random Access Memory） with the Qiangguang-I accelerator in Northwest Institute of Nuclear ...This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM （Partially Depleted Silicon- On-Insulator Static Random Access Memory） with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM （Static Random Access Memory） chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about l×10s Gy（Si）/s. However, there are a few bits upset when the dose rate reaches up to 1.58 x 109 Gy（Si）/s. The SRAM circuit can still work after the high level 3~ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.展开更多
太空中的单粒子效应会对电子器件造成损伤,地面模拟是评估器件抗辐射性能的有效途径。现有的模拟方法大多是基于器件的物理底层模型进行电流源脉冲故障注入,不适用于百万门级大规模集成电路(very large scale integration,VLSI)。针对...太空中的单粒子效应会对电子器件造成损伤,地面模拟是评估器件抗辐射性能的有效途径。现有的模拟方法大多是基于器件的物理底层模型进行电流源脉冲故障注入,不适用于百万门级大规模集成电路(very large scale integration,VLSI)。针对该问题,提出了一种从器件高层行为模型注入单粒子翻转故障的方法,并基于8051 IP核进行了单粒子一位翻转和连续两位翻转的仿真和实验比较。研究结果表明,单粒子翻转故障可直接注入到器件的高层来评估系统的抗单粒子性能。展开更多
文摘This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM （Partially Depleted Silicon- On-Insulator Static Random Access Memory） with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM （Static Random Access Memory） chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about l×10s Gy（Si）/s. However, there are a few bits upset when the dose rate reaches up to 1.58 x 109 Gy（Si）/s. The SRAM circuit can still work after the high level 3~ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.
文摘太空中的单粒子效应会对电子器件造成损伤,地面模拟是评估器件抗辐射性能的有效途径。现有的模拟方法大多是基于器件的物理底层模型进行电流源脉冲故障注入,不适用于百万门级大规模集成电路(very large scale integration,VLSI)。针对该问题,提出了一种从器件高层行为模型注入单粒子翻转故障的方法,并基于8051 IP核进行了单粒子一位翻转和连续两位翻转的仿真和实验比较。研究结果表明,单粒子翻转故障可直接注入到器件的高层来评估系统的抗单粒子性能。
