A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD simulations.The optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the p-pillar.The improved structure is named as SNPPT-MOS.The side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state mode.The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.

Fabrication and characterization of 4H-SiC bipolar junction transistor with double base epilayer

In this paper we report on a novel structure of a 4H-SiC bipolar junction transistor with a double base epilayer that is continuously grown. The measured dc common-emitter current gain is 16.8 at Ic = 28.6 mA （Jc = 183.4 A/cm2）, and it increases with the collector current density increasing. The specific on-state resistance （Rsp-on） is 32.3 mΩ.cm2 and the open-base breakdown voltage reaches 410 V. The emitter N-type specific contact resistance and N＋ emitter layer sheet resistance are 1.7× 10-3 Ω.cm2 and 150 Ω/□, respectively.