Based on the nullor equivalent model of the ideal op amp, the solvability of RLC op amp networks are discussed and some practical problems are analyzed. Then several necessary and sufficient topological conditions for...Based on the nullor equivalent model of the ideal op amp, the solvability of RLC op amp networks are discussed and some practical problems are analyzed. Then several necessary and sufficient topological conditions for unique solvability are given and their proofs are shown in detail.These conditions have great applications in the analysis, synthesis and diagnosis of networks. Finally the solvability of an illustrative network are analyzed as an example.展开更多
This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power const...This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.展开更多
A low-power complementary metal oxide semiconductor（CMOS） operational amplifier （op-amp） for real-time signal processing of micro air vehicle （MAV） is designed in this paper.Traditional folded cascode architectu...A low-power complementary metal oxide semiconductor（CMOS） operational amplifier （op-amp） for real-time signal processing of micro air vehicle （MAV） is designed in this paper.Traditional folded cascode architecture with positive channel metal oxide semiconductor（PMOS） differential input transistors and sub-threshold technology are applied under the low supply voltage.Simulation results show that this amplifier has significantly low power,while maintaining almost the same gain,bandwidth and other key performances.The power required is only 0.12 mW,which is applicable to low-power and low-voltage real-time signal acquisition and processing system.展开更多
Two simple voltage-controlled-oscillators (VCO) with linear tuning laws employing only a single current feedback operational amplifier (CFOA) in conjunction with two analog multipliers (AM) have been highlighted. The ...Two simple voltage-controlled-oscillators (VCO) with linear tuning laws employing only a single current feedback operational amplifier (CFOA) in conjunction with two analog multipliers (AM) have been highlighted. The workability of the presented VCOs has been demonstrated by experimental results based upon AD844 type CFOAs and AD534 type AMs.展开更多
At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed i...At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.展开更多
A high-speed high-accuracy fully differenttial operational amplifier （op-amp） is realized based on no-Miller-capacitor feedforward （NMCF） compensation scheme. In order to achieve a good phase margin, the NMCF comp...A high-speed high-accuracy fully differenttial operational amplifier （op-amp） is realized based on no-Miller-capacitor feedforward （NMCF） compensation scheme. In order to achieve a good phase margin, the NMCF compensation scheme uses the positive phase shift of left-half-plane （LHP） zero caused by the feedforvvard path to counteract the negative phase shift of the non-dominant pole. Compared to traditional Miller compensation method, the op-amp obtains high gain and wide band synchronously without the pole-splitting effect while saves significant chip area due to the absence of the Miller capacitor. Simulated by the 0.35 μm CMOS RF technology, the result shows that the open-loop gain of the op-amp is 118 dB with the unity gain-bandwidth （UGBW） of 1 GHz, and the phase margin is 61°while the settling time is 5.8 ns when achieving 0.01% accuracy. The op-amp is especially suitable for the front-end sample/hold （S/H） cell and the multiplying D/A converter （MDAC） module of the high-speed high-resolution pipelined A/D converters （AVCs）.展开更多
文摘以TSMC0.18μmCMOS制程实现10位元(10-bit)、每秒取样2×107次、操作电压1.8 V的管线式(pipe-line)模拟数字转换器(ADC)芯片。本设计主要是使用1.5-bit/stage架构,并且配合运算放大器(op amp)共享(sharing)技术,拔除传统第一级取样保持放大器(SHA,sample and hold amplifier)以节省功耗。此芯片的量测结果为输入信号频率2 MHz时,输出的SNDR与ENOB各为46.2 dB与7.32-bit,包含焊线垫片(pad)的芯片面积为1.54(1.391×1.107)mm2,芯片功耗为29.2 mW。
文摘Based on the nullor equivalent model of the ideal op amp, the solvability of RLC op amp networks are discussed and some practical problems are analyzed. Then several necessary and sufficient topological conditions for unique solvability are given and their proofs are shown in detail.These conditions have great applications in the analysis, synthesis and diagnosis of networks. Finally the solvability of an illustrative network are analyzed as an example.
基金provided by National Chip Implementation Center(CIC)
文摘This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.
基金Sponsored by the National Natural Science Foundation of China (60843005)the Basic Research Foundation of Beijing Institute of Technology(20070142018)
文摘A low-power complementary metal oxide semiconductor（CMOS） operational amplifier （op-amp） for real-time signal processing of micro air vehicle （MAV） is designed in this paper.Traditional folded cascode architecture with positive channel metal oxide semiconductor（PMOS） differential input transistors and sub-threshold technology are applied under the low supply voltage.Simulation results show that this amplifier has significantly low power,while maintaining almost the same gain,bandwidth and other key performances.The power required is only 0.12 mW,which is applicable to low-power and low-voltage real-time signal acquisition and processing system.
文摘Two simple voltage-controlled-oscillators (VCO) with linear tuning laws employing only a single current feedback operational amplifier (CFOA) in conjunction with two analog multipliers (AM) have been highlighted. The workability of the presented VCOs has been demonstrated by experimental results based upon AD844 type CFOAs and AD534 type AMs.
文摘At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.
文摘A high-speed high-accuracy fully differenttial operational amplifier （op-amp） is realized based on no-Miller-capacitor feedforward （NMCF） compensation scheme. In order to achieve a good phase margin, the NMCF compensation scheme uses the positive phase shift of left-half-plane （LHP） zero caused by the feedforvvard path to counteract the negative phase shift of the non-dominant pole. Compared to traditional Miller compensation method, the op-amp obtains high gain and wide band synchronously without the pole-splitting effect while saves significant chip area due to the absence of the Miller capacitor. Simulated by the 0.35 μm CMOS RF technology, the result shows that the open-loop gain of the op-amp is 118 dB with the unity gain-bandwidth （UGBW） of 1 GHz, and the phase margin is 61°while the settling time is 5.8 ns when achieving 0.01% accuracy. The op-amp is especially suitable for the front-end sample/hold （S/H） cell and the multiplying D/A converter （MDAC） module of the high-speed high-resolution pipelined A/D converters （AVCs）.
