Four optimal design approaches of high-order finite-impulse response filters based on neural network

Four optimal approaches of high-order finite-impulse response(FIR) digital filters were developed for designing four types filters using neural network algorithms. The solutions were presented as parallel algorithms to approximate the desired frequency response specification. Therefore, these methods avoid matrix inversion, and make a fast calculation of the filter’s coefficients possible. The convergence theorems of these proposed algorithms were presented and proved to illustrate them stable, and the implementation of these methods was described together with some design guidelines. The simulation results show that the ripples of the designed FIR filters are significantly little in the pass-band and stop-band, and the proposed algorithms are of fast convergence.

Design of complex FIR filters with arbitrary magnitude and group delay responses

To design approximately linear-phase complex coefficient finite impulse response （FIR） digital filters with arbitrary magnitude and group delay responses, a novel neural network approach is studied. The approach is based on a batch back-propagation neural network algorithm by directly minimizing the real magnitude error and phase error from the linear-phase to obtain the filter＇s coefficients. The approach can deal with both the real and complex coefficient FIR digital filters design problems. The main advantage of the proposed design method is the significant reduction in the group delay error. The effectiveness of the proposed method is illustrated with two optimal design examples.

基于USB PD 3.0协议的新型双相标记解码电路设计与验证

文章提出一种基于USB PD 3.0协议的新型双相标记解码电路设计并给予验证。通过状态机控制计数器的起始与停止,实现单个数据周期突变25%以内的解码结果的预测和产生;通过有限长单位冲激响应滤波器计算得到解码阈值,支持对周期在增减7.13%范围内变化的、连续13个数据的解码,增大解码范围;增加完善的错误检测机制,提高电路的安全性;增加门控,空闲时关闭解码电路,节约能耗。在Synopsys公司的DC开发平台下,对电路进行仿真验证,结果表明相较参考文献中的解码电路,该文的电路结构更简单,解码准确性更高,电路面积更小,功耗更低,解码的安全性更高。

一种考虑关节跃度约束的实时刀具路径光顺算法

针对机器人加工过程中关节跃度超过约束的问题,提出一种考虑机器人关节跃度约束的刀具路径光顺算法。采用有限冲激响应滤波器插值算法对五轴刀具路径进行光顺处理,一步完成了路径光顺和速度规划。建立了关节与刀具之间的速度、加速度和跃度关系,通过调整时间常数保证了关节跃度不超过约束。考虑机器人关节加速度约束后,该算法计算出的时间常数更小。仿真和实验结果表明该算法能减小关节的跟踪误差,提高机器人的工作稳定性。

LCL型光伏并网逆变器频率自适应控制系统设计

光伏并网过程中出现的电网频率波动会使系统采样频率与电网实际频率的比值不再为整数,导致传统重复控制器的谐振频率偏离电网实际频率,谐波抑制能力下降。针对电网频率波动导致并网系统谐波含量上升、控制精度下降的问题,采用了基于Lagrange插值算法的有限脉冲响应滤波器自适应逼近分数阶延迟,实现了系统对电网频率波动的自适应。结合并网逆变器并网运行仿真,验证了所提控制方法对电网波动的适应性及参数设计的正确性。

基于FIR-MSMA的配电网测频算法

针对配电网中含有谐波、带外干扰及其他严重干扰的同步相量测量问题,提出一种基于有限冲击响应滤波器和M类同步相量测量算法(finite impulse response-M synchrophasor measurement algorithm, FIR-MSMA)相结合的配电网测频算法。该方法利用最小二乘法设计出FIR-1滤波器提取低频信号,在此基础上利用设计的FIR-2滤波器实现频率测量的目的,并分析2种滤波器参数设定的原则。利用Matlab软件编制算法仿真程序,验证所提算法的动态测量性能。结果表明,相比于基于离散傅里叶变换的算法和基于滑动平均滤波器的算法,基于FIR-MSMA的算法具有更强的抗干扰能力和更高的测量精度。

FPGA-Based Efficient Programmable Polyphase FIR Filter

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)

A Fusion Kalman Filter and UFIR Estimator Using the Influence Function Method

In this paper,the Kalman filter(KF)and the unbiased finite impulse response(UFIR)filter are fused in the discrete-time state-space to improve robustness against uncertainties.To avoid the problem where fusion filters may give up some advantages of UFIR filters by fusing based on noise statistics,we attempt to find a way to fuse without using noise statistics.The fusion filtering algorithm is derived using the influence function that provides a quantified measure for disturbances on the resulting filtering outputs and is termed as an influence finite impulse response(IFIR)filter.The main advantage of the proposed method is that the noise statistics of process noise and measurement noise are no longer required in the fusion process,showing that a critical feature of the UFIR filter is inherited.One numerical example and a practice-oriented case are given to illustrate the effectiveness of the proposed method.It is shown that the IFIR filter has adaptive performance and can automatically switch from the Kalman estimate to the UFIR estimates according to operating conditions.Moreover,the proposed method can reduce the effects of optimal horizon length on the UFIR estimate and can give the state estimates of best accuracy among all the compared methods.

Design of Computationally Efficient Sharp FIR Filter Utilizing Modified Multistage FRM Technique for Wireless Communications Systems

Modern wireless communications gadgets demand multi-standard communications facilities with least overlap between different input radio channels. A sharp digital filter of extremely narrow transition-width with lower stop band ripples offers alias-free switching among the preferred frequency bands. A computationally competent low pass filter (LPF) structure based on the multistage frequency response masking (FRM) approach is proposed for the design of sharp finite impulse response (FIR) filters which are suitable for wireless communications applications. In comparison of basic FRM with other existing multistage FRM structures, the proposed structure has a narrow transition bandwidth and higher stop band attenuation with significant reduction in terms of the number of computational steps. A design example is incorporated to demonstrate the efficiency of the proposed approach. Simulation results establish the improvement of the proposed scheme over other recently published design strategies.

AN ITERATIVE ALGORITHM FOR OPTIMAL DESIGN OF NON-FREQUENCY-SELECTIVE FIR DIGITAL FILTERS

This paper proposes a novel iterative algorithm for optimal design of non-frequency-selective Finite Impulse Response(FIR) digital filters based on the windowing method.Different from the traditional optimization concept of adjusting the window or the filter order in the windowing design of an FIR digital filter,the key idea of the algorithm is minimizing the approximation error by succes-sively modifying the design result through an iterative procedure under the condition of a fixed window length.In the iterative procedure,the known deviation of the designed frequency response in each iteration from the ideal frequency response is used as a reference for the next iteration.Because the approximation error can be specified variably,the algorithm is applicable for the design of FIR digital filters with different technical requirements in the frequency domain.A design example is employed to illustrate the efficiency of the algorithm.

Optimal Linear Phase Finite Impulse Response Band Pass Filter Design Using Craziness Based Particle Swarm Optimization Algorithm

An efficient method is proposed for the design of finite impulse response(FIR) filter with arbitrary pass band edge,stop band edge frequencies and transition width.The proposed FIR band stop filter is designed using craziness based particle swarm optimization(CRPSO) approach.Given the filter specifications to be realized,the CRPSO algorithm generates a set of optimal filter coefficients and tries to meet the ideal frequency response characteristics.In this paper,for the given problem,the realizations of the optimal FIR band pass filters of different orders have been performed.The simulation results have been compared with those obtained by the well accepted evolutionary algorithms,such as Parks and McClellan algorithm(PMA),genetic algorithm(GA) and classical particle swarm optimization(PSO).Several numerical design examples justify that the proposed optimal filter design approach using CRPSO outperforms PMA and PSO,not only in the accuracy of the designed filter but also in the convergence speed and solution quality.

High-Speed Fault-Tolerant Finite Impulse Response Digital Filter on Field Programmable Gate Array

Some fast finite impulse response (FIR) filters use a large number of look-up tables (LUTs) to configure distributed random-access memories (RAMs) and save registers. The distributed RAMs store 2M precomputed sums of M permuted operands in order to simplify the accumulation, which lays similarity to the solution of Boolean satisfiability (SAT) problem. In this work, a high-speed fault-tolerant FIR digital filter on field programmable gate array (FPGA) is proposed for hardware implementation. A shift register and an RAM are used to arrange the data flow. Generally, an N-tap digital filter only requires N embedded multipliers on FPGA. The better performance is due to high-radix words and low-latency operations. A 32-tap 8-bit FIR digital filter enjoys a throughput of 9.17 MB/s, taking 109 ns to calculate one convolution. In addition, a fault-tolerant scheme by majority logic is used to correct real-time errors within digital filters.

Continuously Variable Bandwidth Sharp FIR Filters with Low Complexity

In software defined radio (SDR), sharp filters of different bandwidth are required to fine tune the desired channel. This requires different computational resources and large number of filter coefficients. This paper proposes a continuously variable bandwidth sharp finite impulse response (FIR) filter with low distortion and low complexity. For this, a fixed length FIR filter is used with two arbitrary sampling rate converters. This system can be used for both the continuous increase as well as decrease of the effective bandwidth of a filter. The low complexity and sharpness are achieved by using the frequency-response masking (FRM) approach for the design of the fixed length FIR filter. The sharp transition width leads to maximum rejection to channel interference in SDR.

Digital FIR filter design for bio-signal processing system

Recently,real-time processing systems for bio-signal of the muscles generated by the movement of the user have been developed.Finite impulse response(FIR)filter for bio-signal processing in bio-signal process systems is composed of multiple multiplier and adder of high-area.This makes the chip area increase significantly.To solve this problem,a low-area digital FIR filter is proposed in this paper,which can reduce the chip area.

Area and Speed Efficient Implementation of Symmetric FIR Digital Filter through Reduced Parallel LUT Decomposed DA Approach

This brief proposes an area and speed efficient implementation of symmetric finite impulse response (FIR) digital filter using reduced parallel look-up table (LUT) distributed arithmetic (DA) based approach. The complexity lying in the realization of FIR filter is dominated by the multiplier structure. This complexity grows further with filter order, which results in increased area, power, and reduced speed of operation. The speed of operation is improved over multiply-accumulate approach using multiplier less conventional DA based design and decomposed DA based design. Both the structure requires B clock cycles to get the filter output for the input width of B, which limits the speed of DA structure. This limitation is addressed using parallel LUTs, called high speed DA FIR, at the expense of additional hardware cost. With large number of taps, the number of LUTs and its size also becomes large. In the proposed method, by exploiting coefficient symmetry property, the number of LUTs in the decomposed DA form is reduced by a factor of about 2. This proposed approach is applied in high speed DA based FIR design, to obtain area and speed efficient structure. The proposed design offers around 40% less area and 53.98% less slice-delay product (SDP) than the high throughput DA based structure when it’s implemented over Xilinx Virtex-5 FPGA device-XC5VSX95T-1FF1136 for 16-tap symmetric FIR filter. The proposed design on the same FPGA device, supports up to 607 MHz input sampling frequency, and offers 60.5% more speed and 67.71% less SDP than the systolic DA based design.

High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier

In this, today’s world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology, many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed-up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay;area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesized with Xilinx.

基于一种新的三模集的低通FIR数字滤波器设计

本文对低通有限脉冲响应(FIR)数字滤波器的设计进行了研究;在对常用三模集和传统的具有脉冲响应系数的FIR数字滤波器分析的基础上,提出将一种新的三模集应用于低通FIR数字滤波器设计的新方法。该FIR滤波器由多个乘法-累加器单元构成,实现正向转换器、并行算术通道和逆向转换器的功能。正向转换器将一个二进制数编码成一个关于模集的余数表示的数,每个算术通道对模集的每个模进行模乘和累加,逆向转换器将一个余数表示的数解码为其等效的二进制数,算术通道以完全并行的架构工作,从而实现轻量化的计算和简单的结构;最后的仿真实验结果不仅验证了本文提出的设计方法的有效性,而且相比于传统的单向转换设计,本文提出的设计方法有更小的滤波器系数偏差和更好的频率响应等波纹特性。

海洋重力数据处理中的正反FIR滤波算法

数字滤波器是影响海洋重力数据处理成果质量的关键技术之一。该文提出了一种实时正反有限冲击响应(FIR)滤波算法,推导了具有线性相位正反FIR滤波器表达式并设计了实时滤波方案:该算法设计出的滤波器在所有的采样频谱内都满足严格意义上的线性相频特性;基于该算法设计的低通滤波器的阻带衰减大,有利于抑制海洋重力数据中的高频噪声。船载重力试验结果表明,在海洋重力数据处理中上述正反FIR滤波器的滤波器实时性好,滤波效果与事后正反FIR滤波器相当,优于单正向FIR滤波效果。