Designs of 3D Mesh and Torus Optical Network-on-Chips:Topology,Optical Router and Routing Module

As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3D integration has the higher packing density and the shorter wire length. Therefore,the 3D ONoC will have the great potential in the future. In this paper,we first discuss the existing ONoC researches,and then design mesh and torus ONoCs from the perspectives of topology,router,and routing module,with the help of 3D integration. A simulation platform is established by using OPNET to compare the performance of 2D and 3D ONoCs in terms of average delay and packet loss rate. The performance comparison between 3D mesh and 3D torus ONoCs is also conducted. The simulation results demonstrate that 3D integration has the advantage of reducing average delay and packet loss rate,and 3D torus ONoC has the better performance compared with 3D mesh solution. Finally,we summarize some future challenges with possible solutions,including microcosmic routing inside optical routers and highly-efficient traffic grooming.

Strict non-blocking four-port optical router for mesh photonic network-on-chip

We report a strict non-blocking four-port optical router that is used for a mesh photonic network-on-chip on a silicon-on-insulator platform.The router consists of eight silicon microring switches that are tuned by the thermo-optic effect.For each tested rousting state,the signal-to-noise ratio of the optical router is larger than 13.8 dB at the working wavelength.The routing functionality of the device is verified.We perform 40 Gbps nonreturn to zero code data transmission on its 12 optical links.Meanwhile,data transmission using wavelength division multiplexing on eight channels in the C band(from 1525 to 1565 nm)has been adopted to increase the communication capacity.The optical router’s average energy efficiency is 25.52 fJ/bit.The rising times(10%to 90%)of the eight optical switch elements are less than 10μs and the falling times(90%-10%)are less than 20μs.

Five-port silicon optical router based on Mach–Zehnder optical switches for photonic networks-on-chip

With the continuous development of integrated circuits, the performance of the processor has been improved steadily. To integrate more cores in one processor is an effective way to improve the performance of the processor, while it is impossible to further improve the property of the processor by only increasing the clock frequency. For a processor with integrated multiple cores, its performance is determined not only by the number of cores, but also by communication efficiency between them. With more processor cores integrated on a chip, larger bandwidths are required to establish the communication among them. The traditional electrical interconnect has gradually become a bottleneck for improving the performance of multiple-core processors due to its limited bandwidth, high power consumption, and long latency. The optical interconnect is considered as a potential way to solve this issue. The optical router is the key device for realizing the optical interconnect. Its basic function is to achieve the data routing and switching between the local node and the multi-node. In this paper we present a five-port optical router for Mesh photonics network-on-chip. A five-port optical router composed of eight thermally tuned silicon Mach-Zehnder optical switches is demonstrated. The experimental spectral responses indicate that the optical signal-to-noise ratios of the optical router are over 13 dB in the wavelength range of 1525-1565 nm for all of its 20 optical links. Each optical link can manipulate 50 wavelength channels with the channel spacing of 100 GHz and the data rate of 32 Gbps for each wavelength channel in the same wavelength range. The lowest energy efficiency of the optical router is 43.4 fJ/bit.