Ring Oscillator for 60 Meter Bandwidth

The 60-meter band range is tremendously useful in telecommunication,military and governmental applications.The I.T.U.(International Telecommunication Union)required isolationism to former radio frequency services because the various frequency bands are extremely overloaded.The allocation of new frequency bands are a lengthy procedure as well as time taking.As a result,the researchers use bidirectional,amateur radio frequency communication for 60-meter band,usually the frequency slot of 5250-5450 KHz,although the entire band is not essentially obtainable for all countries.For transmission and reception of these frequencies,a local oscillator is used in the mixer unit to generate the local signal for mixing the input and reference signals.For this function different type of oscillators are used.In this paper,a three-stage ring oscillator is designed with 1 V supply.Ring oscillators(RO)is the base to explore like to identifying,specify with modelling resources in the disparity in behaviour of the circuit in terms of industrialized design and layout parameters.This type of oscillators are free from noise as inductor is not used to the circuit as in LC oscillator,Heartly oscillator,Colpitt and tuned oscillators.The present approach of circuit designing,the scaling of CMOS(Complementary Metal Oxide Semiconductor)transistor will moderate,the procedure variability.In the forthcoming article,a ring oscillator with fixed capacitor(1 pF)and with variable capacitors(1 to 100 pF)is analysed.The frequency analysis with different capacitor is performed.The total delay of 3-stage oscillator is 4.82 ns with 5.2 MHz oscillation frequency.The overall Power dissipation of the circuit is 1.852μWat 1 V supply.The simulation analysis is performed on 45 nm CMOS technology with both transistor width are 278 and 420 nm.

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply VDD = 1.8 V, the resulting set of performance parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.

A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes

A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.

Frequency Performance of Ring Oscillators Based on a-IGZO Thin-Film Transistors

Ring oscillators based on indium gallium zinc oxide thin film transistors are fabricated on glass substrates. The oscillator circuit consists of seven delay stages and an output buffer inverter. The element inverter exhibits a voltage gain higher than -6 V/V and a wide output swing close to 85% of the full swing range. The dynamic performance of the ring oscillators is evaluated as a function of supply voltage and at different gate lengths. A maximum oscillation frequency of 0.88MHz is obtained for a supply voltage of 50V, corresponding to a propagation delay of less than 85 ns/stage.

Gate Annealing of an Enhancement-Mode InGaP/AlGaAs/InGaAs PHEMT

For enhancement-mode InGaP/A1GaAs/InGaAs PHEMTs,gate annealing is conducted between gate structures of Ti/Pt/Au and Pt/Ti/Pt/Au. Comparison is made after thermal annealing and an optimum annealing process is ob- tained. Using the structure of Ti/Pt/Au, about a 200mV positive shift of threshold voltage is achieved by thermal annea- ling at 320℃ for 40min in N2 ambient. Finally, a stable and consistent enhancement-mode PHEMT is produced successfully with higher threshold voltage.

A Novel Hybrid DPWM for Digital DC-DC Converters

We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital controller, the proposed DPWM can not only offer temperature/process-independent pulse widths, but also operate at a much higher clock frequency than the existing delay-line/counter DPWM structure. Post-simulation results show that with our DPWM, the system clock frequency reaches 156.9MHz while the worst variation,in a temperature range of 0 to 100℃under all process corners,is only± 9.4%.

Design of logic process based low-power 512-bit EEPROM for UHF RFID tag chip

A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.

A method to improve PUF reliability in FPGAs

Due to the impact of voltage,temperature and device aging,the traditional ring oscillator-based physical unclonable functions(RO-PUF)suffers from a unreliability issue,i.e.,PUF output is subject to a constant change.To improve the reliability of the PUF,a stability test scheme related to the PUF mapping unit is proposed.The scheme uses ring oscillators with multiple complexity and various frequencies as sources of interference,which are placed near the PUF prototype circuit to interfere with it.By identifying and discarding unstable slices whichlead to t e instability of PUF,PUF reliability can be effectively improved.Experimental results show that surrounding logic circuits with multiple complexity and multiple frequencies can identify different unstable slices,a d the higher the complexity,t e more unstable slices are detected.Moreover,compared with newly published PUF literature,t e PUF cicuit possesses better statistical characteristic of randomness and lower resource consumption.W it temperatures varying from 0 to 120 t and voltage fluctuating between 0.85 and 1.2 V,its uniqueness and stability can achieve 49.78%a d 98.00%,respectively,which makes it better for use in t e field of security.

Nanosensitive Silicon Microprobes for Mechanical Detection and Measurements

Nanosensitive mechanical microprobes with CMOS transistors, inverters, inverters cascades and ring oscillators, integrated on the thin silicon cantilevers are presented. Mechanical stress shifts linear, steep switching fragment of the inverters’ electrical characteristics. Microprobes were fabricated with use of the standard CMOS technology (3.5 μm design rules, one level polysilicon gate and one level of the metal interconnections) and relief MEMS technique. Control of the silicon cantilever thickness was satisfactory in the range above the few micrometers. Several computer simulations were done to analyze and optimize transistors location on the cantilever, in respect to the mechanical stress distribution. Results of the microprobes electromechanical tests confirm high deflection sensitivity 1.2 - 1.8 mV/nm and force sensitivity 2.0 - 2.4 mV/nN, both in nano ranges. Microprobes, with the ring oscillators revealed sensitivities 5 - 8 Hz/nm. These microprobes seem to be appropriate for applications in precise chemical and biochemical sensing.

High Performance Ring Oscillators from 10-nm Wide Silicon Nanowire Field-Effect Transistors

We explore 10-nm wide Si nanowire （SiNW） field-effect transistors （FETs） for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio （-10s）, low drain-induced barrier lowering （-30 mV） and low subthreshold swing （-80 mV/decade）. The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain （-148） reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.

Carbon nanotube network film-based ring oscillators with sub l O-ns propagation time and their applications in radio-frequency signal transmission

We have fabricated top-gated ambipolar field-effect transistors （FETs） based on solution-derived carbon nanotube （CNT） network films, and then constructed inverters and ring oscillators （ROs） that can work under supply voltages as low as 0.2 V owing to the high uniformity of the devices. Significant improvements were achieved in the performance of these CNT-based ambipolar FETs and CMOS-like circuits by scaling down the gate length of the CNT FETs and optimizing the device structure and RO layout. In particular, the optimized five-stage RO is shown to present a record high oscillation frequency of up to 17.4 MHz with a propagation time of 5.6 ns at a 12-V working voltage. The CNT film-based ROs were used as carrier-wave generators in radio-frequency systems to demonstrate a complete signal transmission process. These results suggest that CNT thin film-based FETs and integrated circuits may soon find their way to radio-frequency applications with a frequency band of 13.56 MHz.

A 0.5-1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixedsignal SoCs with a wide range of operating frequencies.The design proposes a multi-regulator PLL architecture,in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator,reducing the parasitic noise and spur coupling between different PLL building blocks.Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-fvco/1%-VDD.The design is fabricated in 0.13μm 1.5/3.3 V CMOS technology.The in-band phase noise of -102 dBc/Hz at 1 MHz offset with a spur of less than -45 dBc is measured from 1.25 GHz carrier.The measured RMS jitter of the proposed PLL is 1.72 ps at a 1.25 GHz operating frequency.The total power consumption is 19 mW,and its active area is 0.19 mm^2.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is -120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is -169 dBc/Hz.

A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

Design and validation of high speed true random number generators based on prime-length ring oscillators

This paper presents a wide supply voltage range, high speed true random number generator（TRNG） based on ring oscillators, which have different prime number of inverters. And a simple Von Neumann corrector as post processing is also realized to improve data randomness. Prototypes have been implemented and fabricated in 0.18 μm complementary metal oxide semiconductor（CMOS） technology with a wide range of supply voltage from 1.8 V to 3.6 V. The circuit occupies 4 500 μm2, and dissipates minimum 160 μW of power with sampling frequency of 20 MHz. Output bit rate range is from 100 kbit/s to 20 Mbit/s. Statistical test results, which were achieved from the die Hard battery of tests, demonstrate that output random numbers have a well characteristic of randomness.

Injection-seeded single frequency 2.05μm output by ring cavity optical parametric oscillator

An injection-seeded single-resonant optical parametric oscillator（SROPO） with single frequency nanosecond pulsed 2.05 μm wavelength output is presented. Based on two potassium titanyl phosphate crystals and pumped by a 1064 nm single frequency laser pulse, injection seeding is performed successfully by using the ramp-hold-fire technique in a ring cavity with a bow-tie configuration. The SROPO provides 2.65 m J single frequency signal pulse output with a 17.6 ns pulse duration at a 20 Hz repetition rate. A near-diffraction-limited beam is achieved with a beam quality factor M^2 of about 1.2. The spectrum linewidth of the signal pulse is around 26.4 MHz,which is almost the Fourier-transform-limited value.

Accelerometer Design Using MOS Ring Oscillator

A digital accelerometer is developed by using a ring oscillator(RO)and a mixer.The sensitive unit of the accelerometer is the metal-oxide semiconductor(MOS)ROs located on silicon beams.Based on the piezoresistive effect of the MOS RO,the accelerometer transduces the acceleration into frequency output.The syntonic frequency of the MOS RO changes in relation to many environmental elements,such as temperature,source voltage,and so on.The mixer is an interior signal processor that improves the output signal characteristics,with the digital output signal representing the frequency change.As the accelerometer is based on the piezoresistive effect of the MOS RO,the frequency characteristics of the MOS RO and its relationship with the acceleration are described.The device has been fabricated using standard integrated circuits processing methods combined with the Micro-Electro-Mechanical Systems process.The characteristics of the sample chip are in agreement with the theoretical predictions.The accelerometer has a high sensitivity of 6.91 kHz/g,a low temperature coefficient,and a simple fabrication process.

Frequency equation for the submicron CMOS ring oscillator using the first order characterization

By utilizing the first order behavior of the device,an equation for the frequency of operation of the submicron CMOS ring oscillator is presented.A 5-stage ring oscillator is utilized as the initial design,with different Beta ratios,for the computation of the operating frequency.Later on,the circuit simulation is performed from 5-stage till 23-stage,with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively.It is noted that the output frequency is inversely proportional to the square of the device length,and when the value of Beta ratio is used as 2.3,a difference of 3.64%is observed on an average,in between the computed and the simulated values of frequency.As an outcome,the derived equation can be utilized,with the inclusion of an empirical constant in general,for arriving at the ring oscillator circuit’s output frequency.

Monolithic three-dimensional integration of aligned carbon nanotube transistors for high-performance integrated circuits

Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dimensional(M3D)integrated circuits(ICs),which have been considered a promising tech-nology to meet the demands of high-bandwidth computing and fully func-tional integration.However,the lack of high-quality CNT materials at the upper layer and a low-parasitic interlayer dielectric(ILD)makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance.In this work,we demonstrate a multilayer stackable process for M3D integration of high-performance aligned carbon nanotube(A-CNT)transistors and ICs.A low-κ(-3)interlayer SiO_(2)layer is prepared from spin-on-glass(SOG)through processes with a highest temperature of 220℃,presenting low parasitic capaci-tance between two transistor layers and excellent planarization to offer an ideal surface for the A-CNT and device fabrication process.A high-quality A-CNT film with a carrier mobility of 650 cm 2 V^(-1)s^(-1)is prepared on the ILD layer through a clean transfer process,enabling the upper CNT FETs fabri-cated with a low-temperature process to exhibit high on-state current(1 mAμm^(-1))and peak transconductance(0.98 mSμm^(-1)).The bottom A-CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication.As a result,5-stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100μm 2,representing the fastest and the most compact M3D ICs to date.