Theoretical Analysis and Computer Simulation of Different Balance Bridge Voltage Controlled Crystal Oscillator

Q -double effect of different balance bridge voltage controlled crystal oscillator (DBVCXO) is quantitatively analysed by the computer simulation

Statistical Characteristics of Partial Discharge Caused by Typical Defects in Cable Joint under Oscillating Voltage

The oscillating voltage test is a nondestructive detection method for partial discharge of XLPE （cross linked polyethylene） cable and has been applied recently. This paper made three kinds of varying severity artificial defect models of cable joints in 10 kV XLPE cable. Oscillating voltage is applied to the model, by use of pulse current method to detect partial discharge signals. In order to study the statistical characteristics of partial discharge of cable joint under the oscillating voltage, three-dimensional statistical map has been made. The results show that for the same kind of defects, with the increases of the defect severity, the discharge interval extended, the magnitude and the number of partial discharge increase, for different kinds of defects, obvious differences exist among the maps, this may established a foundation for the further study of the partial discharge pattern recognition of XLPE cable under oscillating voltage.

Wideband CMOS LC VCO design and phase noise analysis

A wideband LC cross-coupled voltage controlled oscillator（VCO） is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor（CMOS） technology. Band switching capacitors are adopted to extend the frequency tuning range, and the phase noise is optimized in the design procedure. The functional relationships between the phase noise and the transistors＇ width-length ratios are deduced by a linear time variant （LTV） model. The theoretical optimized parameter value ranges are determined. To simplify the calculation, the working region is split into several sub-ranges according to transistor working conditions. Thus, a lot of integrations are avoided, and the phase noise function upon the design variables can be expressed as simple proportion formats. Test results show that the DC current is 8.8 mA under a voltage supply of 1.8 V; the frequency range is 1.17 to 1.90 GHz, and the phase noise reaches - 83 dBc/Hz at a 10 kHz offset from the carrier. The chip size is 1. 2 mm × 0. 9 mm.

A Fractional-N CMOS DPLL with Self-Calibration

A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.

Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.

A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes

A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.

A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications

A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.

2.7-4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.

A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application

A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.

0.15-μm T-gate In_(0.52)Al_(0.48)As/In_(0.53)Ga_(0.47)As InP-based HEMT with fmax of 390 GHz

In this paper, 0.15-μm gate-length In0.52Al0.48As/In0.53Ga0.47As InP-based high electron mobility transistors （HEMTs） each with a gate-width of 2×50 μm are designed and fabricated. Their excellent DC and RF characterizations are demonstrated. Their full channel currents and extrinsic maximum transconductance （gm,max） values are measured to be 681 mA/mm and 952 mS/mm, respectively. The off-state gate-to-drain breakdown voltage （BVGD） defined at a gate current of-1 mA/mm is 2.85 V. Additionally, a current-gain cut-off frequency （fT） of 164 GHz and a maximum oscillation frequency （fmax） of 390 GHz are successfully obtained; moreover, the fmax of our device is one of the highest values in the reported 0.15-μm gate-length lattice-matched InP-based HEMTs operating in a millimeter wave frequency range. The high gm,max, BVGD, fmax, and channel current collectively make this device a good candidate for high frequency power applications.

A Low Phase Noise, Low Power and Wide Tuning Range VCO with Filtering Technique in ISM Band

In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems applications. For improving the phase noise, filtering technique is used and VCO is designed with TSMC CMOS 0.18 μm technology and the power supply is 1.5 V. The simulation results with advanced design system (ADS) shows that phase noise in 1 MHz offset frequency from the carrier is -122 dBc/Hz and tuning range is 2 to 2.8 GHz. The power consumption of the core is 2.49 mW.

Transient Characteristics and Accommodative Current Limiting Strategy for Bidirectional Interlinking Converters in Hybrid AC/DC Microgrids

Bidirectional interlinking converter(BIC)is the core equipment in a hybrid AC/DC microgrid connected between AC and DC sub-grids.However,the variety of control modes and flexible bidirectional power flow complicate the influence of AC faults on BIC itself and on DC sub-grid,which potentially threaten both converter safety and system reliability.This study first investigates AC fault influence on the BIC and DC bus voltage under different BIC control modes and different pre-fault operation states,by developing a mathematical model and equivalent sequence network.Second,based on the analysis results,a general accommodative current limiting strategy is proposed for BIC without limitations to specific mode or operation condition.Current amplitude is predicted and constrained according to the critical requirements to protect the BIC and relieving the AC fault influence on the DC bus voltage.Compared with conventional methods,potential current limit failure and distortions under asymmetric faults can also be avoided.Finally,experiments verify feasibility of the proposed method.

High voltage generator circuit with low power and high efficiency applied in EEPROM

This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage（V_（th）） MOSFET and the charge transfer switch（CTS） charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48μW and a higher pumping efficiency（83.3%） than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.

An efficient PSP-based model for optimized cross-coupled MOSFETs in voltage controlled oscillator

This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity.The simulation convergence is greatly improved by this method.An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement.The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting.The model is verified with an LC VCO design,and exhibits excellent convergence during simulation.The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(RF) circuit design.

High performance of low voltage controlled ring oscillator with reverse body bias technology

In complementary metal oxide semiconductor （CMOS） nanoscalc technology, power dissipation is becoming important metric. In this work low leakage voltage controlled ring oscillator circuit system was proposed for critical communication systems with high oscillation frequency. An ideal approach has been presented with substrate biasing technique for reduction of power consumption. The simulation have been completed using cadence virtuoso 45 nm standard CMOS technology at room temperature 27~C with supply voltage Vc^d = 0.7 V. The simulation results suggest that voltage controlled ring oscillator has characterized with efficient low power voltage controlled oscillator （VCO） in term of minimum leakage power （1.23 nW） and maximum oscilla- tion frequency （4.76 GHz） with joint positive channel metal oxide semiconductor and negative channel metal oxide semiconductor （PMOS and NMOS） reverse sub- strate bias technique. PMOS, NMOS and joint reverse body bias techniques have been compared in the presented work.

Digitally controlled oscillator design with a variable capacitance XOR gate

A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.

IC design of low power, wide tuning range VCO in 90 nm CMOS technology

A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET（IMOS） varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range（FTR） of 18.4%and a phase noise of –101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator （VCO） with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS （I-MOS） capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process, and the chip area is 1.0 ×0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6,35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz. The figure of merit of the proposed VCO is -192.13 dBc/Hz.

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.

A 3 to 5 GHz low-phase-noise fractional-N frequency synthesizer with adaptive frequency calibration for GSM/PCS/DCS/WCDMA transceivers

A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 #m CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.