Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

Laser-Induced Single Event Transients in Local Oxidation of Silicon and Deep Trench Isolation Silicon-Germanium Heterojunction Bipolar Transistors

We present a study on the single event transient （SET） induced by a pulsed laser in different silicon-germanium （SiGe） heterojunction bipolar transistors （HBTs） with the structure of local oxidation of silicon （LOCOS） and deep trench isolation （DTI）. The experimental results are discussed in detail and it is demonstrated that a SiGe HBT with the structure of LOCOS is more sensitive than the DTI SiGe HBT in the SET. Because of the limitation of the DTI structure, the charge collection of diffusion in the DTI SiGe HBT is less than that of the LOCOS SiGe HBT. The SET sensitive area of the LOCOS SiGe HBT is located in the eollector-substrate （C/S） junction, while the sensitive area of the DTI SiGe HBT is located near to the collector electrodes.

High-voltage SOI lateral MOSFET with a dual vertical field plate

A new silicon-on-insulator （SOI） power lateral MOSFET with a dual vertical field plate （VFP） in the oxide trench is proposed. The dual VFP modulates the distribution of the electric field in the drift region, which enhances the internal field of the drift region and increases the drift doping concentration of the drift region, resulting in remarkable improvements in breakdown voltage （BV） and specific on-resistance （Ron,sp）. The mechanism of the VFP is analyzed and the characteristics of BV and Ron,sp are discussed. It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V, and the Ron,sp decreases from 366 mΩ·cm2 to 110 mΩ·cm2.

A high-voltage SOI MOSFET with a compensation layer on the trenched buried oxide layer

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.