A novel low specific on-resistance （Ron,sp） silicon-on-insulator （SO1） p-channel lateral double-diffused metal-oxide semiconductor （pLDMOS） compatible with high voltage （HV） n-channel LDMOS （nLDMOS） is propo...A novel low specific on-resistance （Ron,sp） silicon-on-insulator （SO1） p-channel lateral double-diffused metal-oxide semiconductor （pLDMOS） compatible with high voltage （HV） n-channel LDMOS （nLDMOS） is proposed. The pLDMOS is built in the N-type SO1 layer with a buried P-type layer acting as a current conduction path in the on-state （BP SOl pLD- MOS）. Its superior compatibility with the HV nLDMOS and low voltage （LV） complementary metal-oxide semiconductor （CMOS） circuitry which are formed on the N-SOl layer can be obtained. In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping, leading to an enhanced （reduced） surface field （RESURF） effect. The proposed BP SO1 pLDMOS achieves not only an improved breakdown voltage （BV） but also a significantly reduced Ron,sp. The BV of the BP SO1 pLDMOS increases to 319 V from 215 V of the conventional SO1 pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ.cm2 to 55 mΩ.cm2. Compared with the PW SO1 pLDMOS, the BP SO1 pLDMOS also reduces the Ron,sp by 34% with almost the same BV.展开更多
基金supported by the National Natural Science Foundation of China (Grant No. 61176069)the State Key Laboratory Science Fund of Electronic Thin Films and Integrated Devices of China (Grant No. CXJJ201004)the National Key Laboratory Science Fund of Analog Integrated Circuit,China (Grant No. 9140C090304110C0905)
文摘A novel low specific on-resistance （Ron,sp） silicon-on-insulator （SO1） p-channel lateral double-diffused metal-oxide semiconductor （pLDMOS） compatible with high voltage （HV） n-channel LDMOS （nLDMOS） is proposed. The pLDMOS is built in the N-type SO1 layer with a buried P-type layer acting as a current conduction path in the on-state （BP SOl pLD- MOS）. Its superior compatibility with the HV nLDMOS and low voltage （LV） complementary metal-oxide semiconductor （CMOS） circuitry which are formed on the N-SOl layer can be obtained. In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping, leading to an enhanced （reduced） surface field （RESURF） effect. The proposed BP SO1 pLDMOS achieves not only an improved breakdown voltage （BV） but also a significantly reduced Ron,sp. The BV of the BP SO1 pLDMOS increases to 319 V from 215 V of the conventional SO1 pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ.cm2 to 55 mΩ.cm2. Compared with the PW SO1 pLDMOS, the BP SO1 pLDMOS also reduces the Ron,sp by 34% with almost the same BV.
