Mobility enhancement of strained GaSb p-channel metal-oxide-semiconductor field-effect transistors with biaxial compressive strain

Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V.s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxiai compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.

Hot-Carrier Effects on Total Dose Irradiated 65 nm n-Type Metal-Oxide-Semiconductor Field-Effect Transistors

The influence of total dose irradiation on hot-carrier reliability of 65 nm n-type metal-oxide-semiconductor field- effect transistors （nMOSFETs） is investigated. Experimental results show that hot-carrier degradations on ir- radiated narrow channel nMOSFETs are greater than those without irradiation. The reason is attributed to radiation-induced charge trapping in shallow trench isolation （STI）. The electric field in the pinch-off region of the nMOSFET is enhanced by radiation-induced charge trapping in STI, resulting in a more severe hot-carrier effect.

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors （MOS- HFETs） were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 ℃ with the contact resistance approximately 1.6 Ω.mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/A1Ox gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AIGaN/GaN MOS-HFETs.

Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In0.53Ga0.47As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the un- derlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given.

Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metal semiconductor field-effect transistors

An improved structure of silicon carbide metal-semiconductor field-effect transistors （MESFET） is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.

Fabrication and characterization of the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors

In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors （MOSF- FETs） have been fabricated and characterized. A sandwich- （nitridation-oxidation-nitridation） type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.

Modulating p-type doping of two-dimensional material palladium diselenide

The van der Waals heterostructures have evolved as novel materials for complementing the Si-based semiconductor technologies.Group-10 noble metal dichalcogenides(e.g.,PtS_(2),PtSe_(2),PdS_(2),and PdSe_(2))have been listed into two-dimensional(2D)materials toolkit to assemble van der Waals heterostructures.Among them,PdSe_(2) demonstrates advantages of high stability in air,high mobility,and wide tunable bandgap.However,the regulation of p-type doping of PdSe_(2) remains unsolved problem prior to fabricating p–n junction as a fundamental platform of semiconductor physics.Besides,a quantitative method for the controllable doping of PdSe_(2) is yet to be reported.In this study,the doping level of PdSe_(2) was correlated with the concentration of Lewis acids,for example,SnCl_(4),used for soaking.Considering the transfer characteristics,the threshold voltage(the gate voltage corresponding to the minimum drain current)increased after SnCl_(4) soaking treatment.PdSe_(2) transistors were soaked in SnCl_(4) solutions with five different concentrations.The threshold voltages from the as-obtained transfer curves were extracted for linear fitting to the threshold voltage versus doping concentration correlation equation.This study provides in-depth insights into the controllable p-type doping of PdSe_(2).It may also push forward the research of the regulation of conductivity behaviors of 2D materials.

基于LSTM-DHMM的MOSFET器件健康状态识别与故障时间预测

针对MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)器件故障预测与健康管理问题,提出了一种长短时记忆(Long Short-Term Memory,LSTM)算法与离散隐马尔可夫模型(Discrete Hidden Markov Model,DHMM)相结合的故障预测新方法.该方法利用LSTM算法预测器件状态发展趋势;用自回归(AutoRegressive,AR)模型提取故障信息特征;以DHMM建立特征向量和退化等级之间的映射关系;在LSTM-DHMM模型预测结果的基础上,结合失效阈值排除虚警并预测故障时间,预测误差小于10%,精度较高.与GRU-DHMM(Gated Recurrent Unit Discrete Hidden Markov Model)、GRU-SVM(Gated Recurrent Unit Support Vector Machine)、LSTM-SVM(Long Short-Term Memory Support Vector Machine)方法进行对比分析,结果表明,LSTM-DHMM的预测准确率高于其他三种方案,能有效识别实验器件健康状态、较好预测故障时间,具有有效性和优越性.

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey（s-Si/s-SiGe/Si1-yGey） metal-oxide-semiconductor field-effect transistor （PMOSFET）, analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel （compressive strained SiGe） than in the surface channel （tensile strained Si）, because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor （MOSFET） designs.

1200V/30 A SiC MOSFET的结构设计与特性仿真

4H-SiC金属氧化物半导体场效应管(metal-oxide-semiconductor field-effect transistor,MOSFET)具有开关频率高、功率密度大、耐高温、抗辐照等优点,在军用和民用领域具有广阔的应用前景。针对漏源击穿电压1 200 V的设计目标,利用解析模型和数值仿真相结合的优化方法,通过分析元胞结构参数对器件电学特性的影响,确定4H-Si C MOSFET元胞的纵向与横向结构参数。仿真结果表明,优化设计的器件其特征导通电阻为4.75 m?·cm2,击穿电压为1 517 V,满足设计指标。

Strain induced changes in performance of strained-Si/strained-Si1-yGey/relaxed-Si1-xGex MOSFETs and circuits for digital applications

Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO_2 /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.

Experimental clarification of orientation dependence of germanium PMOSFETs with Al_2O_3/GeO_x/Ge gate stack

An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is （110）〉（111） ~ （100）, and the best channel direction is （110）/[110]. Moreover, the （110） device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while （100） and （111） devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.

A study of GaN MOSFETs with atomic-layer-deposited Al_2O_3 as the gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect transistors （MOSFETs） with atomic-layer- deposited A1203 gate dielectrics are fabricated. The device, with atomic-layer-deposited A1203 as the gate dielectric, presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm, which are better than those reported previously with Al203 as the gate dielectric. Furthermore, the device shows negligible current collapse in a wide range of bias voltages, owing to the effective passivation of the GaN surface by the A1203 film. The gate drain breakdown voltage is found to be about 59.5 V, and in addition the channel mobility of the n-GaN layer is about 380 cm^2/Vs, which is consistent with the Hall result, and it is not degraded by atomic-layer-deposition A1203 growth and device fabrication.

Quantum confinement effects and source-to-drain tunneling in ultra-scaled double-gate silicon n-MOSFETs

By using the linear combination of bulk band （LCBB） method incorporated with the top of the barrier splitting （TBS） model, we present a comprehensive study on the quantum confinement effects and the source-to-drain tunneling in the ultra-scaled double-gate （DG） metal-oxide semiconductor field-effect transistors （MOSFETs）. A critical body thickness value of 5 nm is found, below which severe valley splittings among different X valleys for the occupied charge density and the current contributions occur in ultra-thin silicon body structures. It is also found that the tunneling current could be nearly 100% with an ultra-scaled channel length. Different from the previous simulation results, it is found that the source-to-drain tunneling could be effectively suppressed in the ultra-thin body thickness （2.0 nm and below） by the quantum confinement and the tunneling could be suppressed down to below 5% when the channel length approaches 16 nm regardless of the body thickness.

基于第一性原理的碳化硅界面态机制研究进展

碳化硅(SiC)金属–氧化物–半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)具有低导通电阻及高击穿临界场强等特点,在高压开关器件领域有着较为广阔的应用及发展前景。但由于SiC/SiO_2具有较高的界面态密度,使得器件反型沟道电子迁移率过低,从而严重阻碍SiC器件的广泛应用。为有效地控制界面态,回顾了国内外对SiC/SiO_2界面态的第一性原理研究进展,分析界面态的形成机制,讨论近导带边界中高界面态的根本原因,为SiC器件工艺制备提供理论指导。