To improve the vehicle dynamic performance and ultra-capacitor operating circumstance,this paper studied the multi-current-two-quadrant converter applied to drive high power DC motor in ultra-capacitor electric bus(UC...To improve the vehicle dynamic performance and ultra-capacitor operating circumstance,this paper studied the multi-current-two-quadrant converter applied to drive high power DC motor in ultra-capacitor electric bus(UCEB).Compared with normal current-two-quadrant converter,the multi-current-two-quadrant converter can reduce the motor armature current ripple and the ultra-capacitor current ripple.Moreover,it improves power capabilities,reliability and fault tolerant capability of driving system.After analyzing the structure and working principle of the multi-current-two-quadrant converter,the expressions of armature current ripple and the quantitative relationships between the ultra-capacitor power loss and duty cycle were derived.The simulation and experimental results showed that the multi-current-two-quadrant converter has great advantages in reducing the armature current ripple and ultra-capacitor power loss,which can improve the vehicle performance and overall efficiency.展开更多
This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-an...This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-analog converter （CDAC） and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-W supply and decreases linearly as the frame rate decreases.展开更多
基金Sponsored by the Heilongjiang 11th Five-year Key Project of Scientific and Technological(Grant No.GA06A305)
文摘To improve the vehicle dynamic performance and ultra-capacitor operating circumstance,this paper studied the multi-current-two-quadrant converter applied to drive high power DC motor in ultra-capacitor electric bus(UCEB).Compared with normal current-two-quadrant converter,the multi-current-two-quadrant converter can reduce the motor armature current ripple and the ultra-capacitor current ripple.Moreover,it improves power capabilities,reliability and fault tolerant capability of driving system.After analyzing the structure and working principle of the multi-current-two-quadrant converter,the expressions of armature current ripple and the quantitative relationships between the ultra-capacitor power loss and duty cycle were derived.The simulation and experimental results showed that the multi-current-two-quadrant converter has great advantages in reducing the armature current ripple and ultra-capacitor power loss,which can improve the vehicle performance and overall efficiency.
基金Project supported by the National Natural Science Foundation of China(No.61234003)the Special Funds for Major State Basic Research Project of China(No.2011CB932902)
文摘This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-analog converter （CDAC） and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-W supply and decreases linearly as the frame rate decreases.
