Iterative Decoding of Parallel Concatenated Block Codes and Coset Based MAP Decoding Algorithm for F24 Code

A multi dimensional concatenation scheme for block codes is introduced, in which information symbols are interleaved and re encoded for more than once. It provides a convenient platform to design high performance codes with flexible interleaver size. Coset based MAP soft in/soft out decoding algorithms are presented for the F24 code. Simulation results show that the proposed coding scheme can achieve high coding gain with flexible interleaver length and very low decoding complexity.

Parallelizing a Code for Counting and Computing Eigenvalues of Complex Tridiagonal Matrices and Roots of Complex Polynomials

A code developed recently by the authors, for counting and computing the eigenvalues of a complex tridiagonal matrix, as well as the roots of a complex polynomial, which lie in a given region of the complex plane, is modified to run in parallel on multi-core machines. A basic characteristic of this code (eventually pointing to its parallelization) is that it can proceed with: 1) partitioning the given region into an appropriate number of subregions;2) counting eigenvalues in each subregion;and 3) computing (already counted) eigenvalues in each subregion. Consequently, theoretically speaking, the whole code in itself parallelizes ideally. We carry out several numerical experiments with random complex tridiagonal matrices, and random complex polynomials as well, in order to study the behaviour of the parallel code, especially the degree of declination from theoretical expectations.

New Parallel Interference Cancellation for Convolutionally Coded CDMA Systems

Based on BCJR algorithm proposed by Bahlet al and linear soft decision feedback, a reduced-complexity parallel interference cancellation (simplified PIC) for convolutionally coded DS CDMA systems is proposed. By computer simulation, we compare the simplified PIC with the exact PIC. It shows that the simplified PIC can achieve the performance close to the exact PIC if the mean values of coded symbols are linearly computed in terms of the sum of initiala prior log-likelihood rate (LLR) and updateda prior LLR, while a significant performance loss will occur if the mean values of coded symbols are linearly computed in terms of the updateda prior LLR only. Meanwhile, we also compare the simplified PIC with MF receiver and conventional PICs. The simulation results show that the simplified PIC dominantly outperforms the MF receiver and conventional PICs, at signal-noise rate (SNR) of 7 dB, for example, the bit error rate is about 10?4 for the simplified PIC, which is far below that of matched-filter receiver and conventional PIC. Key words convolutionally coded CDMA - parallel interference cancellation - BCJR CLC number TN 914 Foundation item: Supported by the National Natural Science Foundation of China (69772015)Biography: Xu Guo-xiong (1967-), male, Ph. D candidate, research direction: wireless communication.

A reordered first fit algorithm based novel storage scheme for parallel turbo decoder

In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput （40-100 Mbps）, the hardware cost is still affordable for 3GPP＇s （3rd generation partnership project） interleaver.

Modified overlapped partly parallel decode for AR4JA codes in deep space communication

In this paper, according to the AR4JA codes in deep space communication, two kinds of iterative decoding including partly parallel decoding and overlapped partly parallel decoding are analyzed, and the advantages and disadvantages of them are listed. A modified overlapped partly parallel decoding that not only inherits the advantages of the two algorithms, but also overcomes the shortcomings of the two algorithms is proposed. The simulation results show that the three kinds of decoding have the same decoding performance; modified overlapped partly parallel decoding improves the iterative convergence rate and the throughput of system.

A Novel Decoder Based on Parallel Genetic Algorithms for Linear Block Codes

Genetic algorithms offer very good performances for solving large optimization problems, especially in the domain of error-correcting codes. However, they have a major drawback related to the time complexity and memory occupation when running on a uniprocessor computer. This paper proposes a parallel decoder for linear block codes, using parallel genetic algorithms (PGA). The good performance and time complexity are confirmed by theoretical study and by simulations on BCH(63,30,14) codes over both AWGN and flat Rayleigh fading channels. The simulation results show that the coding gain between parallel and single genetic algorithm is about 0.7 dB at BER = 10﹣5 with only 4 processors.

正交-响应面法在PBM细观参数标定中的应用

数值模拟作为研究岩石力学特性、再现细观裂纹演化的主要途径,已受到大量关注。现有的数值模拟参数标定方法主要为试错法及正交试验法,但二者都未能充分考虑细观参数交互作用的影响,模拟精度欠佳且宏观破坏形态与室内试验存在较大差异。因此,采用正交-响应面法相结合的数值分析方法,首先通过正交试验筛选出具有显著影响的平行黏结模型(PBM)细观参数,其次应用响应面法(RSM)研究其交互作用对模型试样宏观参量的影响规律,最后结合岩石宏观破坏形态提出一套PBM参数标定流程。结果表明:有效模量E*与刚度比k n/k s对弹性模量E影响显著;k n/k s、接触摩擦系数μ、最小颗粒半径R_(min)对泊松比ν影响显著;黏聚力c与法向黏结强度σc及其交互作用对单轴抗压强度UCS影响显著,应用响应面法计算分析得出的细观参数的模拟值与试验值误差绝对值小于7%,且二者应力应变曲线力学特征相似,宏观破坏形态相同,证明所提出的PBM细观参数标定流程具备科学性和可靠性。

Gamma-Gamma信道下基于并行交织极化码的误码性能研究

为了降低大气湍流引起的衰落影响,同时减少长片误码干扰,提出一种基于并行交织极化码(polar code)的编码方法。通过蒙特卡洛模拟Gamma-Gamma分布的随机数构建大气湍流信道,以成对差错概率(pairwise error probability, PEP)和极化谱确定极化信道的误差概率上限,采用乘积距离准则最小化差错概率,建立了并行交织的设计准则。对极化码在湍流信道中的误码率(bit error rate, BER)性能进行了评估,仿真结果表明,基于极化码的并行交织方法获得了一个量级的误码性能提升,在信噪比为5 dB时,误码率从5.11×10-6降低为2.13×10-7,有效缓解了湍流引起的长片误码问题。实验验证了所提准则的可靠性和适用性。

基于源码分析的自动化外部函数接口生成方法

外部函数接口(FFI)是解决一种编程语言调用其他语言函数库的主要方法。针对使用FFI技术时需要大量人工编码的问题,提出自动化外部函数接口生成(AFIG)方法。该方法利用基于抽象语法树的源码逆向分析技术,从被封装的库文件中精准提取出用于描述函数接口信息的多语言融合的统一表示。基于此统一表示,不同平台的代码生成器可利用多语言转换规则矩阵,全自动化地生成不同平台的FFI相关代码。为解决FFI代码生成中的效率低下问题,设计了一种基于依赖分析的任务聚合策略,通过把存在依赖的任务聚合为新的任务,有效消除了FFI代码任务在并行下的阻塞与死锁,从而实现任务在多核系统下的可扩展与负载均衡。实验结果表明:与人工编码相比,AFIG方法减少了FFI开发中98.14%的开发编码量以及41.95%的测试编码量;与现有的SWIG(Simplified Wrapper and Interface Generator)方法相比,在同等任务下可减少61.27%的开发成本;且生成效率随着计算资源的增加呈线性增长。

高速通信系统中并行CRC计算及电路实现

针对高位宽数据情况下的循环冗余校验码(Cyclic Redundancy Code, CRC)电路计算工作频率较低以及资源占用过多的问题,设计并实现了一种并行CRC计算方法。该方法将CRC计算拆分为数据CRC计算和余数CRC计算两个部分,余数CRC计算由多个余数CRC计算模块级联完成,数据CRC计算模块由固定逻辑表达式实现,对二者计算结果做模二加法即得到CRC计算结果。根据数据长度选择相应的数据CRC计算模块和余数CRC计算模块的组合,以适应高位宽可变数据长度的CRC计算。以100 Gbps远程直接数据存取(Remote Direct Memory Access, RDMA)通信系统中的1 024 bits数据位宽CRC-32的计算为例,在VCU118开发板上实现了该算法的硬件电路。实验结果表明,所提设计仅使用4 760个查找表和2 658个触发器,整个系统带宽最高可达97.85 Gbps,最高工作频率可达326 MHz。与其他相关方法相比,提出的方法具有较高的工作频率且资源占用较少。

分布式存储中基于动态局部修复码的负载均衡研究

分布式存储系统中数据的访问存在不均衡性,大多数访问聚集在少部分数据上,便会引起系统的负载不均衡,导致部分高负载节点成为整个系统的性能瓶颈。针对此问题提出一种负载均衡的动态局部修复码(ALRC),该编码方案通过历史热度对冷热数据进行优先级确立,再对冷热数据进行动态编码,使其具备(r,t)-availability性质,让数据能够拥有额外的访问路径,借此提高热数据的并行访问性能和系统的负载均衡性,同时兼顾一定的存储效率。实验结果表明,ALRC在系统负载较不均衡时只需要相较于编码前少量的额外存储开销,便可拥有相较于原方案53%以上负载均衡度的提升,从而确保节点间的负载分布均匀,提高整个系统的性能和可靠性。

基于领域分析的结构线性静力软件串并行一致化方法

并行CAE软件的计算结果串并行一致性是其计算结果可信的必要条件。然而,软件研发时常引入串并行不一致缺陷,其形式众多,现象相互耦合,散布于海量代码中,成为实现CAE软件串并行一致性的挑战。文中以结构线性静力软件的串并行一致性需求为切入点,针对现有的“专家知识法”与“缺陷定位法”应用于CAE软件串并行一致化时存在的粒度粗、准度差、成本高和缺乏系统性问题,引入领域分析方法,并与专家知识和数据流状态比对结合,提出了一种适用于结构线性静力的串并行一致化方法,实现了结构线性静力软件串并行不一致缺陷的细粒度、高准度与低成本系统性识别与修复。基于前述方法形成相关工具,并将方法与工具应用于SSTA的串并行一致化,识别并修复其中8处串并行不一致缺陷,使其通过90余真实模型的串并行一致考核,并实现串并行结果严格一致;同时,该方法与工具还将串并行不一致缺陷定位耗时由平均大于两人天降低至数人时。

北斗卫星船载导航信号并行捕获算法

信号捕获作为实现北斗卫星船载导航的第一阶段,也是最重要的一环,为此研究基于北斗卫星船载导航信号并行捕获算法,在短时间内捕获卫星信号,为船舶提供高精度的定位和导航服务。建立北斗卫星导航信号模型,依据模型生成的北斗卫星导航信号,采用傅里叶变换(Fast Fourier Transformation,FFT)算法以及快速傅里叶逆变换(Inverse Fast Fourier Transform,IFFT)算法,通过并行频率搜索和并行码相位搜索分别将伪随机码相位、载波频移的二维搜索变成一维进行并行搜索,获取北斗卫星信号的伪随机码和载波频移,实现北斗卫星船载导航信号并行捕获。实验结果表明,该算法可以成功地捕获船载导航信号,并且捕获耗时短;对船载导航信号的载波频率估计误差小。

Impacts of optimization strategies on performance,power/energy consumption of a GPU based parallel reduction

In the era of modern high performance computing, GPUs have been considered an excellent accelerator for general purpose data-intensive parallel applications. To achieve application speedup from GPUs, many of performance-oriented optimization techniques have been proposed. However, in order to satisfy the recent trend of power and energy consumptions, power/energy-aware optimization of GPUs needs to be investigated with detailed analysis in addition to the performance-oriented optimization. In this work, in order to explore the impact of various optimization strategies on GPU performance, power and energy consumptions, we evaluate performance and power/energy consumption of a well-known application running on different commercial GPU devices with the different optimization strategies. In particular, in order to see the more generalized performance and power consumption patterns of GPU based accelerations, our evaluations are performed with three different Nvdia GPU generations(Fermi, Kepler and Maxwell architectures), various core clock frequencies and memory clock frequencies. We analyze how a GPU kernel execution is affected by optimization and what GPU architectural factors have much impact on its performance and power/energy consumption. This paper also categorizes which optimization technique primarily improves which metric(i.e., performance, power or energy efficiency). Furthermore, voltage frequency scaling(VFS) is also applied to examine the effect of changing a clock frequency on these metrics. In general, our work shows that effective GPU optimization strategies can improve the application performance significantly without increasing power and energy consumption.

Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication

In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.

Using Pipeline Instructions by Parallel Simulation of Mathematical Models

Simulation is an important and useful technique helping users understand and model real life systems. Once built, the models can run proving realistic results. This supports making decisions on a more logical and scientific basis. The paper introduces method of simulation, and describes various types of its application. The authors used the method of analysis of the creation and implementation of the programme code. The authors compared parallel instruction of computing defined to pipelined instructions. The power of simulation is that a common model can be used to design a large variety of systems. An important aspect of the simulation method is that a simulation model is designed to be repeated in actual computer systems, especially in multicore processors. For this reason, it is important to minimize average waiting time for fetch and decode stage instructions. The objective of the research is to prove that the parallel operation of programme code is faster than sequential operation code on the multi processor architecture. The system modeling uses methods and simulation on the parallel computer systems is very precise. The time benefit gained in simulation of mathematical model on the pipeline processor is higher than the one in simulation of mathematical model on the multi processors computer system.

Turbo Coded OFDM with Large Number of Subcarriers

Wireless communication systems have greatly advanced during the last years. A significant contributor in these systems’ performance has been Orthogonal Frequency Division Multiplexing (OFDM). Since its invention, it is considered to be a technological leap. This leap in splitting an information stream in multiple frequency carriers has been adapted by various scientists working on the development of wireless systems. Moreover, as OFDM presented excellent tolerance of channel fading and noise signals, the evolvement in terms of speed and reliability was consequent, because only a small stream of information is lost due to noise effects. OFDM along with the knowledge that Turbo codes is another excellent scheme of reducing BER, has triggered us to expand our research. So, we experimented in simulation level not only in joining OFDM with Turbo Codes but even in finding a better Turbo scheme compared to a typical PCCC, SCCC and a Convolutional encoder with Viterbi decoder. As the last goal has already been accomplished, in this paper is presented the new OFDM system consisted of our Turbo scheme. The analysis of the previous system took into consideration the effects of an AWGN channel. Also, this noise analysis was conducted using a simulation platform with specific attributes such as transmitting and receiving fixed number of subcarriers (2048 carriers after IFFT block) while using different types of convolutional concatenated codes, such as PCCC (Parallel), SCCC (Serial) and the new PCCC scheme. The results clearly show not only the improvement in the BER performance of the Turbo Coded OFDM systems (compared to others consisted of Viterbi decoders) but the overall superiority of the proposed design.

Reducing Peak-to-Average Power Ratio of a Turbo Coded OFDM

Peak to Average Power Ratio (PAPR) is defined as the instantaneous power (maximum value) to the average power ratio. PAPR is considered to be a major problem in OFDM systems. This problem can cause radical unexpected behavior of the signal fluctuation. This fluctuation is constituted by a large number of power states. The enormous number of these states leads to an additional complexity of ADCs and DACs. This research addresses the previous problem in OFDM systems utilizing Turbo Codes. μLaCP technique is employed for the purpose of decreasing PAPR. Moreover, our OFDM system was simulated in the presence of an AWGN channel with four types of codes (without the presence of ADCs and DACs). These were constituted of PCCC (typical and new), SCCC, and Convolutional Codes. Our Turbo Coded OFDM exhibited unchanged BER performance before and after the use of μLaCP technique. This was accomplished by modifying our previous PAPR reduction technique without sacrificing greatly its attributes.

面向申威异构架构的并行代码自动生成

异构架构逐渐成为高性能计算领域的主流架构,但相较于同构多核架构,其硬件结构及存储层次更为复杂,程序编写更为困难.先进的优化编译器可以协助程序开发人员实现更为高效的代码,降低程序开发复杂度.多面体编译模型通过抽象分析将程序抽象成空间多面体表示形式,能够将多种循环变换与硬件映射相结合,并面向特定体系结构生成相应的代码.设计实现了一个面向国产申威异构架构的并行代码自动生成系统,采用“源-源”编译模式,基于多面体编译模型实现.系统针对申威异构架构特点将程序计算过程进行硬件部署,同时实现数据传输与内存空间的自动管理.实验基于Polybench测试集中线性代数相关用例进行测试.结果表明,利用代码自动生成系统生成的异构并行代码能够在申威异构平台上正确运行,并能够有效发挥申威异构平台的性能,基于申威异构平台利用64线程加速计算的平均加速比达到了539.16倍.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.