Design and implementation of LDPC encoder based on FPGA

A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.

DB-DCAFN:dual-branch deformable cross-attention fusion network for bacterial segmentation

Sputum smear tests are critical for the diagnosis of respiratory diseases. Automatic segmentation of bacteria from spu-tum smear images is important for improving diagnostic efficiency. However, this remains a challenging task owing to the high interclass similarity among different categories of bacteria and the low contrast of the bacterial edges. To explore more levels of global pattern features to promote the distinguishing ability of bacterial categories and main-tain sufficient local fine-grained features to ensure accurate localization of ambiguous bacteria simultaneously, we propose a novel dual-branch deformable cross-attention fusion network (DB-DCAFN) for accurate bacterial segmen-tation. Specifically, we first designed a dual-branch encoder consisting of multiple convolution and transformer blocks in parallel to simultaneously extract multilevel local and global features. We then designed a sparse and deformable cross-attention module to capture the semantic dependencies between local and global features, which can bridge the semantic gap and fuse features effectively. Furthermore, we designed a feature assignment fusion module to enhance meaningful features using an adaptive feature weighting strategy to obtain more accurate segmentation. We conducted extensive experiments to evaluate the effectiveness of DB-DCAFN on a clinical dataset comprising three bacterial categories: Acinetobacter baumannii, Klebsiella pneumoniae, and Pseudomonas aeruginosa. The experi-mental results demonstrate that the proposed DB-DCAFN outperforms other state-of-the-art methods and is effective at segmenting bacteria from sputum smear images.

General Galois Processor for Transmitters in 5G/6G Base Stations

This paper proposes a flexible eight-mode high parallel Galois SIMD ASIP(Application Specific Instruction Set Processor).It supports parallel executions of Gold,Scrambling,CRC,CC,Turbo,RM,PSS,SSS encoding LFSR(linear feedback shift registers)algorithms with high performance and flexibility.It can perform also general bit processing and m-sequence.Our design is based on proposed table conversion and a datapath for unified eight-mode encoding.Based on 28 nm digital CMOS technology,the total area is 0.177 mm2 and the clock frequency can be up to 1 GHz.The throughputs of Gold,Scrambling,CRC32,CRC24,CRC16,CRC8,CC,Turbo are 64 Gb/s,64 Gb/s,128 Gb/s,168 Gb/s,256 Gb/s,512 Gb/s,3×80 Gb/s,and 72 Gb/s,respectively.

Optimizing a Parallel Video Encoder with Message Passing and a Shared Memory Architecture

Implementing video applications on emerging multi-core processors is a promising technique for personal, real-time multi-media applications. However, when porting the legacy parallel video encoders developed for clusters to shared-memory multi-cores, the existing parallel algorithms result in workload imbalances on different cores and communication inefficiencies. This paper describes a strip-wise parallel scheme to balance workloads and a hybrid communication mechanism to reduce communication overhead. The implementation of the H.264 parallel encoder on an eight CPU Intel Xeon system achieves 5x to 6x speed-up over a single thread encoder and achieves a 29% performance improvement over the commonly used master-slave schemes on clusters. The paper also gives further analysis on scalability, parallel efficiency, workload balance, and communication overhead as the number of cores varies.