Evolutionary Neural Architecture Search and Its Applications in Healthcare

Most of the neural network architectures are based on human experience,which requires a long and tedious trial-and-error process.Neural architecture search(NAS)attempts to detect effective architectures without human intervention.Evolutionary algorithms(EAs)for NAS can find better solutions than human-designed architectures by exploring a large search space for possible architectures.Using multiobjective EAs for NAS,optimal neural architectures that meet various performance criteria can be explored and discovered efficiently.Furthermore,hardware-accelerated NAS methods can improve the efficiency of the NAS.While existing reviews have mainly focused on different strategies to complete NAS,a few studies have explored the use of EAs for NAS.In this paper,we summarize and explore the use of EAs for NAS,as well as large-scale multiobjective optimization strategies and hardware-accelerated NAS methods.NAS performs well in healthcare applications,such as medical image analysis,classification of disease diagnosis,and health monitoring.EAs for NAS can automate the search process and optimize multiple objectives simultaneously in a given healthcare task.Deep neural network has been successfully used in healthcare,but it lacks interpretability.Medical data is highly sensitive,and privacy leaks are frequently reported in the healthcare industry.To solve these problems,in healthcare,we propose an interpretable neuroevolution framework based on federated learning to address search efficiency and privacy protection.Moreover,we also point out future research directions for evolutionary NAS.Overall,for researchers who want to use EAs to optimize NNs in healthcare,we analyze the advantages and disadvantages of doing so to provide detailed guidance,and propose an interpretable privacy-preserving framework for healthcare applications.

New multi-DSP parallel computing architecture for real-time image processing

The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is presented. It has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility. The parallel system performance is evaluated by practical experiment.

Using redundant parallel architecture to improve speaker recognition performance

In this paper, we propose two kinds of modifications in speaker recognition. First, the correlations between frequency channels are of prime importance for speaker recognition. Some of these correlations are lost when the frequency domain is divided into sub-bands. Consequently we propose a particularly redundant parallel architecture for which most of the correlations are kept. Second, generally a log transformation used to modify the power spectrum is done after the filter-bank in the classical spectrum calculation. We will see that performing this transformation before the filter bank is more interesting in our case. In the processing of recognition, the Gaussian mixture model （GMM） recognition arithmetic is adopted. Experiments on speech corrupted by noise show a better adaptability of this approach in noisy environments, comoared with a conventional device, esoeciallv when oruning of some recognizers is performed.

A Content-Based Parallel Image Retrieval System on Cluster Architectures

We propose a content-based parallel image retrieval system to achieve high responding ability. Our system is developed on cluster architectures. It has several retrieval. servers to supply the service of content-based image retrieval. It adopts the Browser/Server (B/S) mode. The users could visit our system though web pages. It uses the symmetrical color-spatial features (SCSF) to represent the content of an image. The SCSF is effective and efficient for image matching because it is independent of image distortion such as rotation and flip as well as it increases the matching accuracy. The SCSF was organized by M-tree, which could speedup the searching procedure. Our experiments show that the image matching is quickly and efficiently with the use of SCSF. And with the support of several retrieval servers, the system could respond to many users at mean time. Key words content-based image retrieval - cluster architecture - color-spatial feature - B/S mode - task parallel - WWW - Internet CLC number TP391 Foundation item: Supported by the National Natural Science Foundation of China (60173058)Biography: ZHOU Bing (1975-), male, Ph. D candidate, reseach direction: data mining, content-based image retrieval.

Parallel Extraction of Marine Targets Applying OIDA Architecture

Computing resources are one of the key factors restricting the extraction of marine targets by using deep learning.In order to increase computing speed and shorten the computing time,parallel distributed architecture is adopted to extract marine targets.The advantages of two distributed architectures,Parameter Server and Ring-allreduce architecture,are combined to design a parallel distributed architecture suitable for deep learning–Optimal Interleaved Distributed Architecture(OIDA).Three marine target extraction methods including OTD_StErf,OTD_Loglogistic and OTD_Sgmloglog are used to test OIDA,and a total of 18 experiments in 3categories are carried out.The results show that OIDA architecture can meet the timeliness requirements of marine target extraction.The average speed of target parallel extraction with single-machine 8-core CPU is 5.75 times faster than that of single-machine single-core CPU,and the average speed with 5-machine 40-core CPU is 20.75 times faster.

Architecture Singularity Analysis of 4-U■S/U■U 5-DOF Parallel Mechanism

Architecture singularity of a parallel mechanism with five degrees of freedom (DOF) is analyzed. Such mechanism consists of a movable platform connected to the base by five active limbs. Four of them are identical 6-DOF limbs and the last one has the same DOF as the specified DOF of the movable platform. Based on the kinematics analysis, two categories of architecture singularities for such mechanism are proposed. Then the sufficient condition for each singularity is researched. Results show that the mechanism is singular when it employs each category of the proposed architecture, provided that it satisfies the corresponding sufficient condition. It can be concluded that the proposed two categories of architecture singularities should be avoided with the following dimensional synthesis of such mechanism.

The Implementation of Ray Tracing Algorithm with OpenMP Parallelization

Ray tracing is a computer graphics method that renders images realistically. As the name suggests, this technique primarily traces the path of light rays interacting with objects in a scene [1], permitting the calculation of lighting and reflecting impact [2]. As ray tracing is a time-consuming process, the need for parallelization to solve this problem arises. One downside of this solution is the existence of race conditions. In this work, we explore and experiment with a different, well-known solution for this race condition. Starting with the introduction and the background section, a brief overview of the topic is followed by a detailed part of how the race conditions may occur in the case of the ray tracing algorithm. Continuing with the methods and results section, we have used OpenMP to parallelize the Ray tracing algorithm with the different compiler directives critical, atomic, and first-private. Hence, it concluded that both critical and atomic are not efficient solutions to produce a good-quality picture, but first-private succeeded in producing a high-quality picture.

Locality Aware Optimal Task Scheduling Algorithm for TriBA —— A Novel Scalable Architecture

An optimal algorithmic approach to task scheduling for, triplet based architecture（TriBA）, is proposed in this paper. TriBA is considered to be a high performance, distributed parallel computing architecture. TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors. In parallel or distributed environment an efficient assignment of tasks to the processing elements is imperative to achieve fast job turnaround time. Moreover, the sojourn time experienced by each individual job should be minimized. The arriving jobs are comprised of parallel applications, each consisting of multiple-independent tasks that must be instantaneously assigned to processor queues, as they arrive. The processors independently and concurrently service these tasks. The key scheduling issues is, when some queue backlogs are small, an incoming job should first spread its tasks to those lightly loaded queues in order to take advantage of the parallel processing gain. Our algorithmic approach achieves optimality in task scheduling by assigning consecutive tasks to a triplet of processors exploiting locality in tasks. The experimental results show that tasks allocation to triplets of processing elements is efficient and optimal. Comparison to well accepted interconnection strategy, 2D mesh, is shown to prove the effectiveness of our algorithmic approach for TriBA. Finally we conclude that TriBA can be an efficient interconnection strategy for computations intensive applications, if tasks assignment is carried out optimally using algorithmic approach.

Designing a Security Architecture for a P2P Video Conference System

More and more modern group oriented collaborativeapplications use the peer-to-peer(P2P)paradigm tobe independent of expensive infrastructures as theyare,for instance,provided for audio and video conferencesby H.323 systems.Decentralized collaborativeP2P solutions require appropriate mechanismsto protect group privacy and data integrity.A centralizedclient/server based video conference system canbe well shielded in a standard manner,whilst thereare no off-the-shelf approaches to secure a P2P videoconference up to now.The paper addresses this issueand presents a flexible security architecture.Usingthe BRAVIS system[4]as an example it shows howthe architecture can be embedded into a P2P videoconferencing system.

Compute Unified Device Architecture Implementation of Euler/Navier-Stokes Solver on Graphics Processing Unit Desktop Platform for 2-D Compressible Flows

Personal desktop platform with teraflops peak performance of thousands of cores is realized at the price of conventional workstations using the programmable graphics processing units(GPUs).A GPU-based parallel Euler/Navier-Stokes solver is developed for 2-D compressible flows by using NVIDIA′s Compute Unified Device Architecture(CUDA)programming model in CUDA Fortran programming language.The techniques of implementation of CUDA kernels,double-layered thread hierarchy and variety memory hierarchy are presented to form the GPU-based algorithm of Euler/Navier-Stokes equations.The resulting parallel solver is validated by a set of typical test flow cases.The numerical results show that dozens of times speedup relative to a serial CPU implementation can be achieved using a single GPU desktop platform,which demonstrates that a GPU desktop can serve as a costeffective parallel computing platform to accelerate computational fluid dynamics(CFD)simulations substantially.

The Methodology of Application Development for Hybrid Architectures

This paper provides an overview of the main recommendations and approaches of the methodology on parallel computation application development for hybrid structures. This methodology was developed within the master＇s thesis project ＂Optimization of complex tasks＇ computation on hybrid distributed computational structures＂ accomplished by Orekhov during which the main research objective was the determination of＂ patterns of the behavior of scaling efficiency and other parameters which define performance of different algorithms＇ implementations executed on hybrid distributed computational structures. Major outcomes and dependencies obtained within the master＇s thesis project were formed into a methodology which covers the problems of applications based on parallel computations and describes the process of its development in details, offering easy ways of avoiding potentially crucial problems. The paper is backed by the real-life examples such as clustering algorithms instead of artificial benchmarks.

Sorting Data Elements by SOCD Using Centralized Diamond Architecture

Several parallel sorting techniques on different architectures have been studied for many years. Due to the need for faster systems in today＇s world, parallelism can be used to accelerate applications. Nowadays, parallel operations are used to solve computer problems such as sort and search, which result in a reasonable speed. Sorting is one of the most important operations in computing world. The authors always try to find the best in different areas which the premier is speedup. In this paper, the authors issued a sort with O（logn） time complexity on PRAM EREW （Parallel Random Access Machine Exclusive Read Exclusive Write）. The algorithm is designed in a manner that keeps the tradeoff between the number of processor elements in the architecture and execution time. The simulation of the algorithm proves the theoretical analysis of the algorithm. The results of this research can be utilized in developing faster embedded systems. Sorting on Centralized Diamond （SOCD） algorithm is issued on the novel Centralized Diamond architecture which takes the advantages of Single Instruction Multiple Data （SIMD） architecture. This architecture and the sort on it are intuitive and optimal.

面向GPU的地形遮蔽探测并行算法

地形遮蔽算法在军事、民航和气象分析等领域有广泛应用。随着仿真规模的扩大、仿真结果实时性要求越来越高,传统计算模型俨然不能满足当下的实时性要求。为解决这一不足,实现了在统一计算设备架构(CUDA)并行计算平台上的地形遮蔽探测算法,解决了仿真计算速度慢的问题。在CPU端将雷达探测区域内离散采样点的高程数据矩阵化,进而提升高程值在并行化计算中的读取速度。针对雷达仿真计算参数对线程分配方式进行优化,采用循环对比方式对地形遮蔽角的计算进行并行加速。采用设备端线程同步和数据交替传输技术,确保计算结果一致性和最大化利用GPU端计算资源。采用多模式并行化计算模式,使用多线程并行化计算和单线程串行化计算来支撑GPU端计算资源不足时的退化计算,从而保证计算的高可用。实验结果表明,相较于i7-12700H CPU在仿真粒度为3 600条探测波束下的地形遮蔽串行计算和多线程并行计算,在3060 Laptop GPU下分别获取了48倍和17倍加速,为仿真实时性提供了有效的工程解决方案。

基于并行双通道时空网络的流量数据修复技术

流量数据丢失是网络系统中常见的问题,通常由传感器故障、传输错误和存储丢失引起.现有的数据修复方法无法学习流量数据的多维特征,因此本文提出了一种结合双向长短期记忆网络与多尺度卷积网络的双通道并行架构(ST-MFCN)用于填补流量数据的缺失值,同时设计了一种新的对抗性损失函数进一步提高预测精度,该模型有效地学习流量数据的时间特征和动态空间特征.本文在Web traffic time series数据集上对模型进行测试,并与现有的修复方法进行对比,实验结果表明,ST-MFCN能够减少数据恢复的误差,提升了数据修复的精确度,为网络系统中的流量数据修复提供了一种稳健高效的解决方案.

基于图形处理器的水下目标传递函数多频点处理方法

为了提高水下目标宽带回波的计算速度,本文提出一种基于图形处理器GPU的散射传递函数多频点快速计算解决方案。相较于传统算法中逐个频率点计算的方式,CUDA快速算法充分利用各频点处目标强度的相对独立性,基于GPU的硬件特点,同时计算宽带内的散射声场,从而显著提高了计算效率。本文以潜航器模型为算例,对不同网格数量下模型的目标散射传递函数计算速度进行对比分析。仿真结果表明,相较于传统的CPU串行计算,采用CUDA快速算法能够实现超过80的加速比,有效提高了计算速度。

基于Farrow架构的任意倍重采样的FPGA设计与实现

任意波形发生器通常使用直接数字波形合成技术生成任意波形,然而使用此技术实现可变采样率功能时,需要调整时钟的工作频率,导致输出中存在难以滤除的镜像频率以及硬件实现难度增加;针对上述问题,对基于Farrow架构的任意倍重采样方法进行了研究,在FPGA上进行了固定时钟驱动下的32路并行的任意倍重采样的逻辑设计与实现;并针对逻辑实现中出现的量化误差积累问题,提出了清除累积误差的逻辑实现方案;经实验测试,实现了在187.5 MHz固定时钟驱动下1 ksps~6 Gsps范围的采样率转换,并解决了量化误差积累造成的长时间运行时波形失真的问题。

一种基于多谐振开关槽与Buck-Boost电路的准并联变换器

谐振开关电容变换器具有效率高、体积小、质量轻和易集成等优点,是中间母线变换器的理想拓扑,然而其不足之处在于电压比固定以及软开关特性易受谐振参数容差的影响。该文针对这两个问题,将多谐振开关槽式变换器与四开关Buck-Boost变换器进行结合,提出一种基于准并联架构的中间母线变换器,详细分析变换器的工作原理与电压增益特性。通过推导电流时域表达式详细分析谐振参数容差对变换器的影响,并给出参数设计的方法。该文研究一种合适的控制方式,完成环路补偿设计,实现输出电压的闭环控制。通过仿真和实验对上述理论和解决方案进行验证。

一种基于Yarn云平台的基因启发式多序列比对算法

提出一种基于Yarn云平台的基因启发式多序列比对算法。建立核酸替换等价矩阵作为基因启发式数学模型,构建Yarn云平台逻辑架构,通过对基因数据预处理、基因数据存储、基因序列比对、基因数据管理、基因数据分析等步骤,对数据分类保存,划分错误率较高的长序列,得到多个较短的基因片段。对不同片段实施定位,将其中的变长种子生成,进行骨架构建和孔隙填补,可以实现基因启发式多序列比对。结果表明,设计的算法在不同数据集下处理时间缩短,多序列比对SP(Sum of Pairs)的分值较高,实验验证了该多序列比对方法具有很好的应用价值。

属性关联模型下大数据集群查询仿真

在数据查询过程中,易受冗余数据、服务器异常、虚拟信息等问题的干扰,导致查询时间长、查询稳定性差等现象产生。为了解决上述问题,提出基于属性关联模型的大数据集群查询算法。采用扩展t-SNE算法对大数据集群中的数据节点做降维处理,避免冗余数据对查询过程产生干扰。将降维后的数据输入到属性关联模型中,实现大数据集群的特征提取,并将提取的特征输入到分布式并行架构中,通过查询负载量的计算完成大数据集群的查询。实验结果表明,所提算法的响应时间短,查询开销小于50Mb,且查询稳定性强。