A 12-Channel,30Gb/s,0.18μm CMOS Front-End Amplifier for Parallel Optic-Fiber Receivers

This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier. The experimental results indicate that, with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0. 8mVpp input. Furthermore, an isolation structure combined with a p^＋ guard.ring （PGR）, an n^＋ guard-ring （NGR）,and a deep-n-well （DNW） for parallel amplifier is also presented. Taking this combined structure, the crosstalk and the substrate noise coupling have been effectively reduced. Compared with the isolation of PGR or PGR ＋ NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8. ldB at 1GHz,and by 8. 1 and 2. 5dB at 2GHz,respectively. With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W.

A High Speed,12-Channel Parallel,Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit （OEIC） receiver are reported. Each channel of the receiver consists of a photodetector, a transimpedance amplifier,and a post-amplifier. The double photodiode structure speeds up the receiver but hinders responsivity. The adoption of active inductors in the TIA circuit extends the - 3dB bandwidth to a higher level. The receiver has been realized in a CSMC 0.6μm standard CMOS process. The measured results show that a single channel of the receiver is able to work at bit rates of 0.8- 1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

High performance power-configurable preamplifier in a high-density parallel optical receiver

A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.

A novel satellite-equipped receiver for autonomous monitoring of GNSS navigation signal quality

Global navigation satellite system(GNSS) comes with potential unavoidable application risks such as the sudden distortion or failure of navigation signals because its satellites are generally operated until failure. In order to solve the problems associated with these risks, receiver autonomous integrity monitoring(RAIM) and ground-based signal quality monitoring stations are widely used. Although these technologies can protect the user from the risks, they are expensive and have limited region coverage. Autonomous monitoring of satellite signal quality is an effective method to eliminate these shortcomings of the RAIM and ground-based signal quality monitoring stations; thus, a new navigation signal quality monitoring receiver which can be equipped on the satellite platform of GNSS is proposed in this paper. Because this satellite-equipped receiver is tightly coupled with navigation payload, the system architecture and its preliminary design procedure are first introduced. In theory, code-tracking loop is able to provide accurate time delay estimation of received signals. However, because of the nonlinear characteristics of the navigation payload, the traditional code-tracking loop introduces errors. To eliminate these errors, the dummy massive parallel correlators(DMPC) technique is proposed. This technique can reconstruct the cross correlation function of a navigation signal with a high code phase resolution. Combining the DMPC and direct radio frequency(RF) sampling technology, the satellite-equipped receiver can calibrate the differential code bias(DCB) accurately. In the meantime, the abnormities and failures of navigation signal can also be monitored. Finally, the accuracy of DCB calibration and the performance of fault monitoring have been verified by practical test data and numerical simulation data, respectively. The results show that the accuracy of DCB calibration is less than 0.1 ns and the novel satellite-equipped receiver can monitor the signal quality effectively.