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Design of cable tester based on multi-thread parallel testing technology
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作者 WEN feng YUAN Xiao hang +2 位作者 DING Zhi zhao WANG Xiao li ZHEN Guo yong 《Journal of Measurement Science and Instrumentation》 CAS CSCD 2018年第3期214-218,共5页
In order to realize the efficiency, reliability and safety tests on the complex cable network of an electronic system, an efficient cable network resistance tester is designed. Firstly, the design background and hardw... In order to realize the efficiency, reliability and safety tests on the complex cable network of an electronic system, an efficient cable network resistance tester is designed. Firstly, the design background and hardware structure are briefly described. Then aiming at the multi task parallelism considering real time measurement of parameters and real time control of the system in the tester testing, a real time muhi task control software is developed by using multi thread testing technology in parallel test to realize multi task complex control. Finally, the least squares method is used to improve the test accuracyof the tester. The test results show that the test error is basically within 0.3%, and the test speed can reach 345 point/min. 展开更多
关键词 cable tester multi thread parallel least square method
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Simultaneous Multithreading Fault Tolerance Processor
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作者 DONGLan HUMing-zeng +3 位作者 JIZhen-zhou CUIGuang-zuo TANGXin-min HEFeng 《Wuhan University Journal of Natural Sciences》 EI CAS 2005年第1期17-20,共4页
Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting both ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading (SMT) Fa... Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting both ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading (SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 40%–61%longer than running a single version of the program. The new instruction fetch algorithm enhances the performance by 0.4%~1%to most of the benchmarks we choose randomly. 展开更多
关键词 Key words simultaneous multithreading rault tolerance TLP (Thread Level parallelism) fetch policy
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High Performance General-Purpose Microprocessors: Past and Future 被引量:5
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作者 胡伟武 侯锐 +1 位作者 肖俊华 章隆宾 《Journal of Computer Science & Technology》 SCIE EI CSCD 2006年第5期631-640,共10页
It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to sim... It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors (CMPs). Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced. 展开更多
关键词 high performance general-purpose microprocessor instruction level parallelism data level parallelism thread level parallelism chip multiprocessors Godson processor
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