Parasitic bipolar amplification in a single event transient and its temperature dependence

Using three-dimensional technology computer-aided design （TCAD） simulation, parasitic bipolar amplification in a single event transient （SET） current of a single transistor and its temperature dependence are studied. We quantify the contributions of different current components in a SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both ]30-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of the SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of a single transistor.

New insight into the parasitic bipolar amplification effect in single event transient production

In this paper, a new method is proposed to study the mechanism of charge collection in single event transient （SET） production in 90 nm bulk complementary metal oxide semiconductor （CMOS） technology. We find that different from the case in the pMOSFET, the parasitic bipolar amplification effect （bipolar effect） in the balanced inverter does not exist in the nMOSFET after the ion striking. The influence of the suhstrate process on the bipolar effect is also studied in the pMOSFET. We find that the bipolar effect can be effectively mitigated by a buried deep P＋-well layer and can be removed by a buried SO2 layer.

Experimental verification of the parasitic bipolar amplification effect in PMOS single event transients

The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event charge collection is composed of diffusion, drift, and the parasitic bipolar effect, while for PMOSs in the special layout, the parasitic bipolar junction transistor cannot turn on. Heavy ion experimental results show that PMOSs without parasitic bipolar amplification have a 21.4% decrease in the average SET pulse width and roughly a 40.2% reduction in the SET cross-section.

Temperature dependence of the P-hit single event transient pulse width in a three-transistor inverter chain

A comparison of the temperature dependence of the P-hit single event transient （SET） in a two-transistor （2T） inverter with that in a three-transistor （3T） inverter is carried out based on a three-dimensional numerical simulation. Due to the significantly distinct mechanisms of the single event change collection in the 2T and the 3T inverters, the temperature plays different roles in the SET production and propagation. The SET pulse will be significantly broadened in the 2T inverter chain while will be compressed in the 3T inverter chain as temperature increases. The investigation provides a new insight into the SET mitigation under the extreme environment, where both the high temperature and the single event effects should be considered. The 3T inverter layout structure （or similar layout structures） will be a better solution for spaceborne integrated circuit design for extreme environments.

Analysis of multiple cell upset sensitivity in bulk CMOS SRAM after neutron irradiation

In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up （SEL） sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset （MCU） is the parasitic bipolar amplification, it bring us to study the impact of neutron irradiation on the SRAM＇s MCU sensitivity. After the neutron experiment, we test the devices＇ function and electrical parameters. Then, we use the heavy ion fluence to examine the changes on the devices＇ MCU sensitivity pre- and post-neutron-irradiation. Unfortunately, neutron irradiation makes the MCU phenomenon worse. Finally, we use the electric static discharge （ESD） testing technology to deduce the experimental results and find that the changes on the WPM region take the lead rather than the changes on the parasitic bipolar amplification for the 90 nm process.

Experimental and simulation studies of single-event transient in partially depleted SOI MOSFET

In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.

Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.

Single event transient pulse attenuation effect in three-transistor inverter chain

In this paper, compared with two-transistor (2T) inverter chain, the production and propagation of P-hit single event transient (SET) in three-transistor (3T) inverter chain is studied in depth based on three-dimensional numerical simulations in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology. The pulse attenuation effect is found in 3T inverter chain, and the pulse can not completely propagate through the inverter chain as LET increases. The discovery will provide a new insight into SET hardened design, the 3T inverter layout structure (or similar layout structures) will be a better method in integrated circuits (ICs) design in radiation environment.

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.

Temperature dependence of charge sharing and MBU sensitivity induced by a heavy ion

The temperature dependence of charge sharing in a 130 nm CMOS technology has been investigated over a temperature range of 200 to 420 K.Device simulation results show that the charge sharing collection increases by 66%-325% when the temperature rises.The LETth of a MBU in two SRAM cells and one DICE cell is also quantified.Besides charge sharing, the circuit response＇s temperature dependence also has a significant influence on the LETth.

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout（SEB） hardened planar power MOSFET with partially widened trench sources by three-dimensional（3 D） numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region（P-well region below the N＋ source）. The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer（LET）,which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to0.7 p C/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.