Experimental and simulation studies of single-event transient in partially depleted SOI MOSFET

In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.

Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout（SEB） hardened planar power MOSFET with partially widened trench sources by three-dimensional（3 D） numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region（P-well region below the N＋ source）. The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer（LET）,which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to0.7 p C/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.