According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to ...According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to the test length, thus the reduction of the test length in a scan design is strongly required. In this paper, we propose a partial scan design system at RT level design, named REPS, to reduce the test application time. REPS has the following new features: (1) a scan register selection method at RT level; (2) a DFT database is prepared to estimate test length of blocks; and (3) a DFT strategy generation for the shortest test length. We applied REPS to some test designs for a practical LSI that described at RT level. It is found that REPS estimates an accurate test length for an LSI at RTL, i.e. the error of the length is less than 10% from that at the gate level. As a result, the test length generated by the partial scan design method was 37% shorter than that by the conventional full scan design method.展开更多
选择两条退役110 k V交联聚乙烯电缆A、B及一条备用电缆,利用局部放电、差示扫描量热法(differential scanning calorimetry,DSC)试验、耐压试验、扫描电镜(scanning electron microscope,SEM)试验分析绝缘层老化状态。结果表明,在2U0(U...选择两条退役110 k V交联聚乙烯电缆A、B及一条备用电缆,利用局部放电、差示扫描量热法(differential scanning calorimetry,DSC)试验、耐压试验、扫描电镜(scanning electron microscope,SEM)试验分析绝缘层老化状态。结果表明,在2U0(U0为电缆额定电压)及以下电压,电缆的局部放电量变化小,电压大于2U0后,电缆的局部微小缺陷及劣化大量显现出来,局部放电量大幅增加,但局部放电量与工频耐受电压表明电缆A、B依然符合国家标准。结合DSC试验运行和备用电缆绝缘层热力学参数,最终得到电缆A比电缆B老化严重的结论;SEM试验作为补充,说明了在电缆生产过程中的本体缺陷在后期运行中会扩大,且会加速其绝缘老化。展开更多
文摘According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to the test length, thus the reduction of the test length in a scan design is strongly required. In this paper, we propose a partial scan design system at RT level design, named REPS, to reduce the test application time. REPS has the following new features: (1) a scan register selection method at RT level; (2) a DFT database is prepared to estimate test length of blocks; and (3) a DFT strategy generation for the shortest test length. We applied REPS to some test designs for a practical LSI that described at RT level. It is found that REPS estimates an accurate test length for an LSI at RTL, i.e. the error of the length is less than 10% from that at the gate level. As a result, the test length generated by the partial scan design method was 37% shorter than that by the conventional full scan design method.
文摘选择两条退役110 k V交联聚乙烯电缆A、B及一条备用电缆,利用局部放电、差示扫描量热法(differential scanning calorimetry,DSC)试验、耐压试验、扫描电镜(scanning electron microscope,SEM)试验分析绝缘层老化状态。结果表明,在2U0(U0为电缆额定电压)及以下电压,电缆的局部放电量变化小,电压大于2U0后,电缆的局部微小缺陷及劣化大量显现出来,局部放电量大幅增加,但局部放电量与工频耐受电压表明电缆A、B依然符合国家标准。结合DSC试验运行和备用电缆绝缘层热力学参数,最终得到电缆A比电缆B老化严重的结论;SEM试验作为补充,说明了在电缆生产过程中的本体缺陷在后期运行中会扩大,且会加速其绝缘老化。