This paper introduces a novel verification development platform for the passive UHF RFID tag,which is compatible with the ISO/IEC 18000-6B standard,operating in the 915MHz ISM band. This platform efficiently reduces t...This paper introduces a novel verification development platform for the passive UHF RFID tag,which is compatible with the ISO/IEC 18000-6B standard,operating in the 915MHz ISM band. This platform efficiently reduces the design and development time and cost, and implements a fast prototype design of the passive UHF RFID tag. It includes the RFID analog front end and the tag control logic, which is implemented in an Altera ACEX FPGA. The RFID analog front end, which is fabricated using a Chartered 0.35μm two-poly four-metal CMOS process, contains a local oscillator, power on reset circuit, matching network and backscatter, rectifier, regu- lator,AM demodulator, etc. The platform achieves rapid, flexible and efficient verification and development, and can also be fit for other RFID standards after changing the tag control logic in FPGA.展开更多
Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF v...Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.展开更多
文摘This paper introduces a novel verification development platform for the passive UHF RFID tag,which is compatible with the ISO/IEC 18000-6B standard,operating in the 915MHz ISM band. This platform efficiently reduces the design and development time and cost, and implements a fast prototype design of the passive UHF RFID tag. It includes the RFID analog front end and the tag control logic, which is implemented in an Altera ACEX FPGA. The RFID analog front end, which is fabricated using a Chartered 0.35μm two-poly four-metal CMOS process, contains a local oscillator, power on reset circuit, matching network and backscatter, rectifier, regu- lator,AM demodulator, etc. The platform achieves rapid, flexible and efficient verification and development, and can also be fit for other RFID standards after changing the tag control logic in FPGA.
基金supported by the High Technology Research and Development Program of Tianjin (No. 05YFGZGX02300)
文摘Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.
