A Passive Mixer with Changeable Mixing Mechanism

In this work, a 3D mixer has been conceived based on the splitting and recombining mechanism with simple topology structure. This mixer can present excellent performance at extremely low Reynolds number, which is very important for the practical use. Further research exhibits that the mixing also can be realized via the chaotic advection that occurred at decreased aspect ratio of channel. Thus, the changeable mechanism of mixer shows potential of being used widely. Meanwhile, mixing process has been confirmed in a fabricated structure. The simulated flow patterns reappear in a scaled-up mixer and full mixing can be achieved in 8 mm channel length at varied flow rate. Due to the high efficiency and easy fabrication, this 3D mixer possesses great prospect for a large number of micro- fluidic systems.

A reconfigurable passive mixer for multimode multistandard receivers in 0.18 μm CMOS

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximum IIP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch （I or Q） ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm2 including pads.

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier（TIA）,which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency（RF） ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency（IF） bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure（NF） is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

High linearity current communicating passive mixer employing a simple resistor bias

A high linearity current communicating passive mixer including the mixing cell and transimpedance amplifier(TIA) is introduced.It employs the resistor in the TIA to reduce the source voltage and the gate voltage of the mixing cell.The optimum linearity and the maximum symmetric switching operation are obtained at the same time.The mixer is implemented in a 0.25μm CMOS process.The test shows that it achieves an input third-order intercept point of 13.32 dBm,conversion gain of 5.52 dB,and a single sideband noise figure of 20 dB.

A PMMA Passive Micromixer with Three-Dimensional Tortuous Mixing Chamber

In this paper,we design and fabricate a novel three-dimensional passive-micro-mixer by using Polymethyl methacrylate( PMMA). The mixer is fabricated by using ultra-precision engraving machine and bonded by an organic solvent fumigation bonding method. The mixer combines two fluid streams into a mixing chamber integrated with T-shaped pre-mixing and six tortuous shaped mixing elements. We have employed three-dimensional numerical simulations to evaluate the mixing efficiency. The simulation results indicate,under inlet fluid pressure p = 10( Pa), compared to the planar serpentine mixer and tortuous mixer,the concentration fluctuation range at the outlet diagonal reduce to 48% and 71. 6% respectively. And the mixing concentration variances also show that the mixing efficiency has a significant increase. We characterize the device by using visualization microscope,and the results are consistent with the simulation data. The device demonstrates the promising capabilities for micro total analysis system integration.

An ultra-broadband distributed passive gate-pumped mixer in 0.18μm CMOS

A broadband distributed passive gate-pumped mixer（DPGM） using standard 0.18μm CMOS technology is presented.By employing distributed topology,the mixer can operate at a wide frequency range.In addition,a fourth-order low pass filter is applied to improve the port-to-port isolation.This paper also analyzes the impedance match and conversion loss of the mixer,which consumes zero dc power and exhibits a measured conversion loss of 9.4—17 dB from 3 to 40 GHz with a compact size of 0.78 mm^2.The input referred 1 dB compression point is higher than 4 dBm at a fixed IF frequency of 500 MHz and RF frequency of 23 GHz,and the measured RF-to-LO, RF-to-IF and LO-to-IF isolations are better than 21,38 and 45 dB,respectively.The mixer is suitable for WLAN, UWB,Wi-Max,automotive radar systems and other millimeter-wave radio applications.

A high linearity current mode second IF CMOS mixer for a DRM/DAB receiver

A passive current switch mixer was designed for the second IF down-conversion in a DRM/DAB re- ceiver. The circuit consists of an input transconductance stage, a passive current switching stage, and a current amplifier stage. The input transconductance stage employs a self-biasing current reusing technique, with a resistor shunt feedback to increase the gain and output impedance. A dynamic bias technique is used in the switching stage to ensure the stability of the overdrive voltage versus the PVT variations. A current shunt feedback is introduced to the conventional low-voltage second-generation fully balanced multi-output current converter （FBMOCCII）, which provides very low input impedance and high output impedance. With the circuit working in current mode, the linearity is effectively improved with low supply voltages. Especially, the transimpedance stage can be re- moved, which simplifies the design considerably. The design is verified with a SMIC 0.18μm RF CMOS process. The measurement results show that the voltage conversation gain is 1.407 dB, the NF is 16.22 dB, and the IIP3 is 4.5 dBm, respectively. The current consumption is 9.30 mA with a supply voltage of 1.8 W. This exhibits a good compromise among the gain, noise, and linearity for the second IF mixer in DRM/DAB receivers.

A 3-5 GHz BPSK transmitter for IR-UWB in 0.18μm CMOS

This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system.It is based on up-conversion with a high linearity passive mixer.Unlike the traditional BPSK modulation scheme,the local oscillator （LO） is modulated by the baseband data instead of the pulse.The chip is designed and fabricated by standard 0.18μm CMOS technology.The transmitter achieves a high data rate up to 400 Mbps.The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the driver amplifier.The maximum peak-to-peak amplitude of the pulse is 600 mV.It consumes only 20.3 mA current with a supply voltage of 1.8 V when transmitting a pulse at the maximum data rate.The energy efficiency is 91.4 pJ/pulse.The die area is 1.4×1.4 mm^2.

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

A CMOS long-term evolution(LTE) direct convert receiver that eliminates the interstage SAW filter is presented.The receiver consists of a low noise variable gain transconductance amplifier(TCA),a quadrature passive current commutating mixer with a 25%duty-cycle LO,a trans-impedance amplifier(TIA),a 7th-order Chebyshev filter and programmable gain amplifiers(PGAs).A wide dynamic gain range is allocated in the RF and analog parts.A current commutating passive mixer with a 25%duty-cycle LO improves gain,noise,and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference.Fabricated in a 0.13μm CMOS process,the receiver chain achieves a 107 dB maximum voltage gain,2.7 dB DSB NF(from PAD port),-11 dBm 11P3,and>+65 dBm UP2 after calibration,96 dB dynamic control range with 1 dB steps,less than 2%error vector magnitude(EVM) from 2.3 to 2.7 GHz.The total receiver(total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

A CMOS RF front-end for the long-term evolution（LTE） direct conversion receiver is presented.With a low noise transconductance amplifier（LNA）,current commutating passive mixer and transimpedance operational amplifier（TIA）,the RF front-end structure enables high-integration,high linearity and simple frequency planning for LTE multi-band applications.Large variable gain is achieved using current-steering transconductance stages.A current commutating passive mixer with 25%duty-cycle LO improves gain,noise and linearity.A direct coupled current-input filter（DCF） is employed to suppress the out-of-band interferer.Fabricated in a 0.13-μm CMOS process,the RF front-end achieves a 45 dB conversion voltage gain,2.7 dB NF,-7 dBm IIP3,and ＋60 dBm IIP2 with calibration from 2.3 to 2.7 GHz.The total RF front end with divider draws 40 mA from a single 1.2-V supply.

A high linearity downconverter for SAW-less LTE receivers

This paper presents a high linearity downconverter implemented in a 0.18μm CMOS process for long term evolution（LTE） receivers without a surface acoustic wave（SAW） filter.The proposed downconverter is composed of a transconductance（Gm） stage,a passive mixer,a current buffer,a transimpedance（TIA） stage,and a DC-offset cancellation（DCOC） loop.The current buffer is utilized to provide very low load impedance for the passive mixer at high frequencies and reduce the output voltage swing induced by out-of-band blockers.This technique improves the input referred third-order intercept point（IIP3） and second-order intercept point（IIP2） of the down-converter by 4.5 dB and 11 dB,respectively.The measured results show that the proposed downconverter achieves a voltage conversion gain of 29.5 dB,double sideband noise figure of 12.7 dB,out-of-band IIP3 of 13 dBm and IIP2 of more than 62 dBm.

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.

A wideband large dynamic range and high linearity RF front-end for U-band mobile DTV

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced, and includes a noise-cancelling low-noise amplifier （LNA）, an RF programmable gain amplifier （RFPGA） and a current communicating passive mixer. The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA. An RFPGA with five stages provides large dynamic range and fine gain resolution. A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor, and optimum linearity and symmetrical mixing is obtained at the same time. The RF front-end is implemented in a 0.25 #m CMOS process. Tests show that it achieves an IIP3 （third-order intercept point） of -17 dBm, a conversion gain of 39 dB, and a noise figure of 5.8 dB. The RFPGA achieves a dynamic range of-36.2 to 23.5 dB with a resolution of 0.32 dB.

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consump- tion at low gain mode. The front-end chip is manufactured on a 0.13-#m CMOS process and occupies an active chip area of 1.2 mm2. It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.

A 0.7–7 GHz wideband reconfigurable receiver RF front-end in CMOS

A 0.7–7 GHz wideband RF receiver front-end So C is designed using the CMOS process. The front-end is composed of two main blocks: a single-ended wideband low noise amplifier（LNA） and an in-phase/quadrature（I/Q） voltage-driven passive mixer with IF amplifiers. Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth. The passive down-conversion mixer includes two parts: passive switches and IF amplifiers. The measurement results show that the frontend works well at different LO frequencies, and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency. The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB, a minimum noise figure（NF） of 3.2 dB, with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm;.