The implementation of the coordinate rotational digital computer (CORDIC) algorithm with wave pipelining technique on field programmable gate array (FPGA) is described. All data in FPGA-based wave pipelining pass ...The implementation of the coordinate rotational digital computer (CORDIC) algorithm with wave pipelining technique on field programmable gate array (FPGA) is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.展开更多
In this paper, the balanced economic growth path was considered in a new growth model with endogenous technical progress. It is not only obtained the optimal allocation about capital and labor between a goods-producin...In this paper, the balanced economic growth path was considered in a new growth model with endogenous technical progress. It is not only obtained the optimal allocation about capital and labor between a goods-producing sector and a R&D Sector, but also the optimal value of saving rates. By discussing the effect of parameters, it are also got the following results: When the rate of time preference (discount factor) rising, the fractions of Capital and labor in the goods-producing sector will increase, the fractions in R&D sector and the saving rates will decrease; When the population grows rapidly, the result will be contrary.展开更多
文摘The implementation of the coordinate rotational digital computer (CORDIC) algorithm with wave pipelining technique on field programmable gate array (FPGA) is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.
文摘In this paper, the balanced economic growth path was considered in a new growth model with endogenous technical progress. It is not only obtained the optimal allocation about capital and labor between a goods-producing sector and a R&D Sector, but also the optimal value of saving rates. By discussing the effect of parameters, it are also got the following results: When the rate of time preference (discount factor) rising, the fractions of Capital and labor in the goods-producing sector will increase, the fractions in R&D sector and the saving rates will decrease; When the population grows rapidly, the result will be contrary.