对硅片上自组装生长的Pentacene薄膜生长机制及其结晶相态的研究

采用热蒸发的方法在硅片衬底上自组装生长的Pentacene薄膜,薄膜在80℃温度下经2h恒温真空热处理,通过原子力显微镜(AFM)对Pentacene薄膜表面形貌及其生长机制进行研究。结果得到,在硅片上生长的Pentacene薄膜是以台阶岛状结构生长,其岛状直径约为100nm。且Pentacene分子以垂直于衬底的方向生长,台阶岛状结构中每个台阶的平均高度约为1.54nm.s-1,与Pentacene分子的沿长轴方向的长度相近。从Pentacene薄膜的XRD图谱中可以看出,薄膜在形成的过程中会因条件的不同而形成不同的结晶相,分别为薄膜相和三斜体相,且薄膜的结晶相将随着薄膜厚度的增加向三斜体相转变,其临界厚度为80和150nm,当薄膜大于150nm时,薄膜的三斜体相占主导地位,而当Pentacene薄膜的厚度小于80nm时,Pentacene薄膜呈薄膜相存在。

Pentacene分子的Ballistic传导特性(英文)

在考虑到Pentacene分子的碳原子中的唯一个活跃的π电子的情况下,从理论上研究了两端接有金属电极的Pentacene分子带的Ballistic传导特性.利用相邻原子的HOMO和LUMO之间的小能量级差和相对低的LUMO值,得出了由金属电极桥接的Pentacene分子带的量子传导方程,讨论了金属电极和Pen-tacene分子间界面阻抗对传导性的影响,得出了通过Pentacene分子系统的传导流.

Density Functional Theory Calculations of Charge-Induced Spin Polarization in Pentacene

Based on density functional theory （DFT） calculations, we investigate the spin-related properties of spinless-hole injected organic molecule pentacene （Pc）. DFT calculations reveal that there is spontaneous spin polarization in Pc when spinless-hole is injected. The chargeinduced magnetic moment of Pc increases linearly with the increasing of the extra hole charge amount and its maximum can be up to 1 μB per injected spinless-hole per Pc molecule. The magnetic moment is expected due to the injected unpaired charge. The injected hole will preferably ll the spin-splitted carbon pz orbitals, which makes the Pc molecule spin polarize.

退火时间对溶液法制备Tips-Pentacene电流传输特性的影响

通过测量p+Si/PEDOT∶PSS/Tips-PEN/Ag器件的J-V特性,研究了退火时间对溶液法制备Tips-PEN薄膜电流传输特性的影响。实验结果表明,在退火时间为2h和5h的条件下,随偏置电压的增加,双对数J-V曲线存在斜率依次为2,大于3以及2的不同区域,而在退火时间达到10h后,低电压下斜率为2的区域消失。根据空间电荷限制电流模型,分析了不同区域的电流传输机理,并提取了陷阱密度和空穴的迁移率。在退火时间为10h时,材料有最低的陷阱密度5.70×1018/cm3和最大的空穴迁移率1.68×10-4 cm2/(V·s),其在低偏置下传输特征的改变表明与溶剂残留有关的单一能级陷阱极大减小。

Synthesis,characterization of the pentacene and fabrication of pentacene field-effect transistors

A comprehensive understanding of the organic semiconductor material pentacene is meaningful for organic fieldeffect transistors （OFETs）. Thin films of pentacene are the most mobile molecular films known to date. This paper reported that the pentacene sample was successfully synthesized. The purity of pentacene is up to 95%. The results of a joint experimental investigation based on a combination of infrared absorption spectra, mass spectra （MS）, element analysis, x-ray diffraction （XRD） and atom force microscopy （AFM）. The authors fabricated OFET with the synthesized pentacene. Its field effect mobility is about 1.23 cm^2/（V·s） and on-off ratio is above 10^6.

The effect of annealing temperature and film thicknesson the phase of pentacene on the p^+-Si substrate

This paper investigates the morphology and crystallization properties of the two crystalline phases of pentacene grown by thermal evaporation on p^＋-Si substrates at room temperature by the methods of atomic force microscopy and x-ray diffraction. This kind of substrate induces a thin film phase and a triclinic phase which are formed directly onto p^＋-Si substrates and constitute a layer consisting of faceted grains with a step height between terraces of 15.8A（1A=0.1 nm） and 14.9A, respectively. Above the critical thickness of the thin film phase, lamellar structures are found with an increasing fraction with the increase of the film thickness. When the film thickness is fixed, the fraction of lamellar structures increases with the increase of annealing temperature. These lamellar structures are identified as the second phase with a interplanar distance of 14.9A corresponding to the pentacene triclinic phase. Furthermore, the thin film phase consisting of several micrometre sized uniformly oriented grains at an annealing temperature of less than 80℃ and a deposition rate of 0.6A/s is observed.

Characteristics of pentacene organic thin film transistor with top gate and bottom contact

High performance pentacene organic thin film transistors （OTFT） were designed and fabricated using SiO2 deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass substrate with S-D electrode pattern made from ITO by means of thermal evaporation through self-organized process. The threshold voltage VTH was -2.75±0.1V in 0-50V range, and that subthreshold slopes were 0.42±0.05V/dec. The field-effect mobility （μEF） of OTFT device increased with the increase of VDS, but the μEF of OTFT device increased and then decreased with increased VGS when VDS was kept constant. When VDS was -50V, on/off current ratio was 0.48×10^5 and subthreshold slope was 0.44V/dec. The μEF was 1.10cm^2/（V.s）, threshold voltage was -2.71V for the OTFT device.

Introduction of F_4-TCNQ/MoO_3 layers for thermoelectric devices based on pentacene

We introduced a dual electron accepting layer composed of tetrafluoro-tetracyanoquinodimethane （F4-TCNQ） and MoO3 for thermoelectric devices based on a pentacene layer. We found that the power factor is enhanced by placing an F4-TCNQ layer directly in contact with the pentacene layer and it is also enhanced by placing a MoO3 layer between the F4-TCNQ layer and the Au electrode. By examining the contact resistance using a field effect transistor and a hole-only diode, we confirmed that the hole injection is improved due to the reduction of contact resistance at the interface between the MoO3 layer and the Au electrode.

Remote-Plasma-Assisted Deposition of Pentacene Layer Using Atomic-Hydrogen

Pentacene thin layers were deposited on Si with the native oxide at 80°C by remote-plasma-assisted deposition (RPAD) using hydrogen-plasma cell to supply atomic hydrogen radicals. The deposition rate was increased by RPAD comparing to that by non-excited hydrogen gas supply whereas thermal evaporation rate of pentacene from crucible was same in the both process. DFM and XRD studies showed the grain laterally grew in the thin film phase with the size above 10 μm by RPAD. First-principles molecular orbital calculations suggested pentacene is evaporated from crucible as the trimer or larger cluster but atomic hydrogen penetrated into the cluster enhances cracking of pentacene clusters to the monomer.

Electrical Instability in Pentacene Transistors with Mylar and PMMA/Mylar Gate Dielectrics Transferred by Lamination Process

This study deals with electrical instability under bias stress in pentacene-based transistors with gate dielectrics deposited by a lamination process. Mylar film is laminated onto a polyethylene terephthalate (PET) substrate, on which aluminum (Al) gate is deposited, followed by evaporation of organic semiconductor and gold (Au) source/drain contacts in bottom gate top contact configuration (Device 1). In order to compare the influence of the semiconductor/dielectric interface, a second organic transistor (Device 2) which is different from the Device 1 by the deposition of an intermediate layer of polymethyl methacrylate (PMMA) onto the laminated Mylar dielectric and before evaporating pentacene layer is fabricated. The critical device parameters such as threshold voltage (VT), subthreshold slope (S), mobility (μ), onset voltage (Von) and Ion/Ioff ratio have been studied. The results showed that the recorded hysteresis depend on the pentacene morphology. Moreover, after bias stress application, the electrical parameters are highly modified for both devices according to the regimes in which the transistors are operating. In ON state regime, Device 1 showed a pronounced threshold voltage shift associated to charge trapping, while keeping the μ, Ioff current and S minimally affected. Regardless of whether Device 2 exhibited better electrical performances and stability in ON state, we observed a bias stress-induced increase of depletion current and subthreshold slope in subthreshold region, a sign of defect creation. Both devices showed onset voltage shift in opposite direction.

Lowering the driving voltage and improving the luminance of blue fluorescent organic light-emitting devices by thermal annealing a hole injection layer of pentacene

We chose pentacene as a hole injection layer（HIL） to fabricate the high performance blue fluorescent organic lightemitting devices（OLEDs）. We found that the carrier mobility of the pentacene thin films could be efficiently improved after a critical annealing at temperature 120℃. Then we performed the tests of scanning electron microscopy, atomic force microscopy, and Kelvin probe to explore the effect of annealing on the pentacene films. The pentacene film exhibited a more crystalline form with better continuities and smoothness after annealing. The optimal device with 120℃ annealed pentacene film and n-doped electron transport layer（ETL） presents a low turn-on voltage of 2.6 V and a highest luminance of 134800 cd/m^2 at 12 V, which are reduced by 26% and improved by 50% compared with those of the control device.

Top Contact Pentacene Organic Thin Film Field Effect Transistors

Using pentacene as an active material, the organic thin film transistors were fabricated on Si3N4/p-Si substrates by using RF-magnetron sputtered amorphous aluminium as the gate electrode contact, and using highly doped Si as the gate electrode and substrate with plasma-enhanced chemical vapor deposited （PECVD） silicon nitride as gate dielectric. Pentacene thin films were deposited by thermal evaporation on dielectrics as the active layer, then RF-magnetron sputtered amorphous aluminium was used as the source and drain contacts. Measurement results show that field effect mobility and threshold voltage are 0.043 cm2/（V·s） and 12.6 V, respectively, and on-off current ratio is nearly 1×103.

Influence of Temperature and Pentacene Thickness on the Electrical Parameters in Top Gate Organic Thin Film Transistor

In this contribution, we report on the effect of pentacene thickness and temperature on the performance of top gate transistors. We first investigated the temperature dependence of the transport properties in the temperature range of 258 K - 353 K. The electrical characteristics showed that the threshold voltage (VT) and the onset voltage (Von) remain unchanged. However, the subthreshold current (Ioff), the on-current (Ion) and the field effect mobility (μ) are highly affected with a slight deterioration of subthreshold slope. We observed Arrhenius-like behavior suggesting a thermally activated mobility with an activation energy EA = 68 meV. Moreover the dependence of the charge carrier mobility on the organic semiconductor thickness has also been studied. The mobility decreased as the pentacene thickness increases whereas the threshold voltage and Ioff current remain minimally affected. In order to understand the transport properties and in view to put in light morphology peculiarities of pentacene, AFM images were performed. It turns out that the pentacene grain sizes are smaller and disorganized as the film thickness increases, and charge carriers are more prone to be trapped, leading to decrease the field effect mobility and the Ion current. The devices were also tested under bias stress and the transistors with low thicknesses exhibited a relatively good electrical stability compared to those with high pentacene thicknesses. This work points out the influence of temperature, semiconductor thickness and bias stress effect on the device performance and stability of transistor using top gate configuration.

Optimization of 6,13Bis(triisopropylsilylethynyl)pentacene (TIPS-Pentacene) Organic Field Effect Transistor: Annealing Temperature and Solvent Effects

In this contribution, we report on the effect of solvents with different boiling points and annealing temperature on the performance of TIPS-pentacene transistors. Several solvents have been used for TIPS-pentacene thin film processing: toluene, chlorobenzene and tetrahy-drofuran. To study the influence of solvent and temperature;the electrical parameters of TIPS-pentacene field effect transistor were measured. The highest values of mobilities were 7.1 × 10-3 cm2·V-1·s-1, 4.5 × 10-3?cm2·V-1·s-1 and 1.43 × 10-3 cm2·V-1·s-1 respectively for TIPS-pentacene field effect transistor using chlorobenzene, toluene and tetrahydrofuran and annealed respectively at 120°C, 150°C and 120°C. We have correlated these electrical performances with AFM images in order to point out the role of morphological properties. It is found that the grain size, and roughness highly affect the electrical parameters.

Heterojunction-engineered carrier transport in elevated-metal metal-oxide thin-film transistors

This study investigates the carrier transport of heterojunction channel in oxide semiconductor thin-film transistor(TFT)using the elevated-metal metal-oxide(EMMO)architecture and indium−zinc oxide(InZnO).The heterojunction band diagram of InZnO bilayer was modified by the cation composition to form the two-dimensional electron gas(2DEG)at the interface quantum well,as verified using a metal−insulator−semiconductor(MIS)device.Although the 2DEG indeed contributes to a higher mobility than the monolayer channel,the competition and cooperation between the gate field and the built-in field strongly affect such mobility-boosting effect,originating from the carrier inelastic collision at the heterojunction interface and the gate field-induced suppression of quantum well.Benefited from the proper energy-band engineering,a high mobility of 84.3 cm2·V^(−1)·s^(−1),a decent threshold voltage(V_(th))of−6.5 V,and a steep subthreshold swing(SS)of 0.29 V/dec were obtained in InZnO-based heterojunction TFT.

Indispensable gutter layers in thin-film composite membranes for carbon capture

Industrial thin-film composite(TFC)membranes achieve superior gas separation properties from high-performance selective layer materials,while the success of membrane technology relies on high-performance gutter layers to achieve production scalability and low-cost manufacturing.However,the current literature predominantly focuses on the design of polymer architectures to obtain high permeability and selectivity,while the art of fabricating gutter layers is usually safeguarded by industrial manufacturers and appears lackluster to academic researchers.This is the first report aiming to provide a comprehensive and critical review of state-of-the-art gutter layer materials and their design and modification to enable TFC membranes with superior separation performance.We first elucidate the importance of the gutter layer on membrane performance through modeling and experimental results.Then various gutter layer materials used to obtain high-performance composite membranes are critically reviewed,and the strategies to improve their compatibility with the selective layer are highlighted,such as oxygen plasma treatment,polydopamine deposition,and surface grafting.Finally,we present the opportunities of the gutter layer design for practical applications.

Low-Volatile Binder Enables Thermal Shock-Resistant Thin-Film Cathodes for Thermal Batteries

Manufacturing thin-film components is crucial for achieving high-efficiency and high-power thermal batteries(TBs).However,developing binders with low-gas production at the operating temperature range of TBs(400-550°C)has proven to be a significant challenge.Here,we report the use of acrylic acid derivative terpolymer(LA136D)as a low-volatile binder for thin-film cathode fabrication and studied the chain scission and chemical bondbreaking mechanisms in pyrolysis.It is shown LA136D defers to randomchain scission and cross-linking chain scission mechanisms,which gifts it with a low proportion of volatile products(ψ,ψ=39.2 wt%)at even up to 550°C,well below those of the conventional PVDF(77.6 wt%)and SBR(99.2 wt%)binders.Surprisingly,LA136D contributes to constructing a thermal shock-resistant cathode due to the step-by-step bond-breaking process.This is beneficial for the overall performance of TBs.In discharging test,the thin-film cathodes exhibited a remarkable 440%reduction in polarization and 300%enhancement in the utilization efficiency of cathode materials,while with just a slight increase of 0.05 MPa in gas pressure compared with traditional“thick-film”cathode.Our work highlights the potential of LA136D as a low-volatile binder for thin-film cathodes and shows the feasibility of manufacturing high-efficiency and high-power TBs through polymer molecule engineering.

Implementation of sub-100 nm vertical channel-all-around(CAA) thin-film transistor using thermal atomic layer deposited IGZO channel

In-Ga-Zn-O(IGZO) channel based thin-film transistors(TFT), which exhibit high on-off current ratio and relatively high mobility, has been widely researched due to its back end of line(BEOL)-compatible potential for the next generation dynamic random access memory(DRAM) application. In this work, thermal atomic layer deposition(TALD) indium gallium zinc oxide(IGZO) technology was explored. It was found that the atomic composition and the physical properties of the IGZO films can be modulated by changing the sub-cycles number during atomic layer deposition(ALD) process. In addition, thin-film transistors(TFTs) with vertical channel-all-around(CAA) structure were realized to explore the influence of different IGZO films as channel layers on the performance of transistors. Our research demonstrates that TALD is crucial for high density integration technology, and the proposed vertical IGZO CAA-TFT provides a feasible path to break through the technical problems for the continuous scale of electronic equipment.

Numerical Simulation of Flow Field and Flow State Division in Thin-Film Evaporators

The flow field and flow state of thin-film evaporators are complex,and it is significant to effectively divide and quantify the flow field and flow state,as well as to study the internal flow field distribution and material mixing characteristics to improve the efficiency of thin-film evaporators.By using computational fluid dynamics(CFD)numerical simulation,the distribution pattern of the high-viscosity fluid flow field in the thin-film evaporators was obtained.It was found that the staggered interrupted blades could greatly promote material mixing and transportation,and impact the film formation of high-viscosity materials on the evaporator wall.Furthermore,a flow field state recognition method based on radial volume fraction statistics was proposed,and could quantitatively describe the internal flow field of thin-film evaporators.The method divides the high-viscosity materials in the thin-film evaporators into three flow states,the liquid film state,the exchange state and the liquid mass state.The three states of materials could be quantitatively described.The results show that the materials in the exchange state can connect the liquid film and the liquid mass,complete the material mixing and exchange,renew the liquid film,and maintain continuous and efficient liquid film evaporation.