Set Programming Method and Performance Improvement of Phase Change Random Access Memory Arrays

A novel slow-down set waveform is proposed to improve the set performance and a 1 kb phase change random access memory chip fabricated with a 13nm CMOS technology is implemented to investigate the set performance by different set programming strategies based on this new set pulse. The amplitude difference （I1 - I2） of the set pulse is proved to be a crucial parameter for set programming. We observe and analyze the cell characteristics with different I1 - I2 by means of thermal simulations and high-resolution transmission electron microscopy, which reveal that an incomplete set programming will occur when the proposed slow-down pulse is set with an improperly high I1 - I2. This will lead to an amorphous residue in the active region. We also discuss the programming method to avoid the set performance degradations.

Three-Dimensional Simulations of RESET Operation in Phase-Change Random Access Memory with Blade-Type Like Phase Change Layer by Finite Element Modeling

An optimized device structure for reducing the RESET current of phase-change random access memory （PCRAM） with blade-type like （BTL） phase change layer is proposed. The electrical thermal analysis of the BTL cell and the blade heater contactor structure by three-dimensional finite element modeling are compared with each other during RESET operation. The simulation results show that the programming region of the phase change layer in the BTL cell is much smaller, and thermal electrical distributions of the BTL cell are more concentrated on the TiN/GST interface. The results indicate that the BTL cell has the superiorities of increasing the heating efficiency, decreasing the power consumption and reducing the RESET current from 0.67mA to 0.32mA. Therefore, the BTL cell will be appropriate for high performance PCRAM device with lower power consumption and lower RESET current.

Investigation and solution of low yield problem for phase change memory with lateral fully-confined structure

This paper mainly focuses on solving the low yield problem for lateral phase change random access memory with a fully confined phase change material node. Improper over-etching and bad step-coverage of physical vapor deposition were the main reasons for the poor contact quality, which leads to the low yield problem. Process improvement was carried out to better control over-etching within 10 nm. Atomic layer deposition process was used to replace physical vapor deposition to guarantee good step coverage. Contrasting cross-sectional photos taken by scanning electron microscopy showed great improvement in contact quality. The atom layer deposition process was demonstrated to have good prospects in nano-contact for phase change memory application.

High quality metal-quantum dot-metal structure fabricated with a highly compatible self-aligned process

A self-aligned process to fabricate a ＂metal-quantum dot-metal＂ structure is presented, based on an ＂electron beam lithography, thin film deposition and dry etching process＂. The sacrificial layers used can improve the lift-off process, and novel lithography layouts design can improve the mechanical strength of the fabricated nanostructures. The superiority of the self-aligned process includes low request for overlay accuracy, high compatibility with a variety of materials, and applicable to similar structure devices fabrication. Finally, a phase change memory with fully confined phase-change material node, with the length × width × height of 255 × 45 × 30 nm^3 was demonstrated.