In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparison...In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparisons are made. A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop （PLL） is designed. The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the LIP and DN signals to be logic-1 simultaneously. Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL. Furthermore, it has hardly any dead-zone phenomenon in phase characteristic. Simulations with ADS are performed based on a TSMC 0. 18-μm CMOS process with a 1.8-V supply voltage. According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency （≈ 1 GHz）, a wide phase-detection range [ ± 2π], a near zero dead-zone （ 〈 0. 1 ps）, high reliability, low phase jitter, low power consumption （ ≈100 μW） and small circuit complexity.展开更多
Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor netwo...Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor networks（WSNs）.The PFD can compare the frequency and phase differences of input signals and deliver a signal voltage proportional to the difference.Low threshold transistors are used in the circuits since a power supply of 0.5V is adopted.A pulse latched structure is also used in the circuits in order to increase both the detection range of phase errors and the maximum operation frequency.In experiments,a phase error with a range from-358° to 358° is measured when the input signal frequency is 2MHz.The PFD has a faster acquisition speed compared with conventional digital PFDs.When the input signals are at a frequency of 2MHz with zero phase error,the circuits have a power consumption of 1.8[KG＊8]μW,and the maximum operation frequency is 1.25GHz.展开更多
A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum re...A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.展开更多
The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phas...The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phase detector （FD＆PD） is described. A new automatic frequency band selection （FBS） without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.展开更多
A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel...A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.展开更多
Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eli...Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.展开更多
A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase fr...A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.展开更多
文摘In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparisons are made. A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop （PLL） is designed. The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the LIP and DN signals to be logic-1 simultaneously. Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL. Furthermore, it has hardly any dead-zone phenomenon in phase characteristic. Simulations with ADS are performed based on a TSMC 0. 18-μm CMOS process with a 1.8-V supply voltage. According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency （≈ 1 GHz）, a wide phase-detection range [ ± 2π], a near zero dead-zone （ 〈 0. 1 ps）, high reliability, low phase jitter, low power consumption （ ≈100 μW） and small circuit complexity.
基金The National High Technology Research and Development Program of China (863 Program) (No. 2007AA01Z2A7)Program for Special Talents in Six Fields of Jiangsu Province
文摘Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor networks（WSNs）.The PFD can compare the frequency and phase differences of input signals and deliver a signal voltage proportional to the difference.Low threshold transistors are used in the circuits since a power supply of 0.5V is adopted.A pulse latched structure is also used in the circuits in order to increase both the detection range of phase errors and the maximum operation frequency.In experiments,a phase error with a range from-358° to 358° is measured when the input signal frequency is 2MHz.The PFD has a faster acquisition speed compared with conventional digital PFDs.When the input signals are at a frequency of 2MHz with zero phase error,the circuits have a power consumption of 1.8[KG＊8]μW,and the maximum operation frequency is 1.25GHz.
文摘A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.
基金supported by the Hubei Natural Science Foundation of China underGrant No. 2010CDB02706the Fundamental Research Funds for the Central Universities under Grant No. C2009Q060
文摘The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phase detector （FD＆PD） is described. A new automatic frequency band selection （FBS） without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.
基金Funded by the Communication System Project of Jiangsu Provincial Education Committee under grant No.JHB04010
文摘A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.
基金Project supported by the National Basic Research Program of China(No.2010CB327404)the National High Technology Research and Development Program(No.2011AA10305)the National Natural Science Foundation of China(No.60901012)
文摘Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.
基金supported by the National Natural Science Foundation of China(No.41274047)the Natural Science Foundation of Jiangsu Province(No.BK2012639)+2 种基金the Foundation of Suzhou City(No.SYG201135)the Science and Technology Enterprises in Jiangsu Province Tech-nology Innovation Fund(No.BC2012121)the Changzhou Science and Technology Support Program(Industrial)(No.CE20120074)
文摘A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.
