RF phase jitter is a very important parameter for a relativistic klystron amplifier. This parameter is closely linked with the physics processes in the klystron. RF phase jitter is theoretically studied together with ...RF phase jitter is a very important parameter for a relativistic klystron amplifier. This parameter is closely linked with the physics processes in the klystron. RF phase jitter is theoretically studied together with Particle in Cell （PIC） simulations in the paper. The main factor is deduced and verified in the PIC simulation. RF phase jitter is significantly affected by the fluctuation of the beam voltage. The relation between the phase jitter and the voltage fluctuation is linear in certain ranges.展开更多
In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation ...In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation frequencies, we calculate additional time jitters of these dividers by using the measured phase noise. The time jitters are various from -0.1 fs to 43 fs in a bandwidth from 1 Hz to 100 Hz in dependent of models and operation frequencies. The HMC series frequency dividers exhibit outstanding performance for high operation frequencies, and the time jitters can be sub-fs. The time jitters of SP8401, MC10EP139, and MC100LVEL34 are comparable or even below that of HMC series for low operation frequencies.展开更多
抗干扰雷达长期以来是雷达领域的研究热点,数字射频存储器(Digital Radio Frequency Memory,DRFM)技术通过转发最大程度模拟真实目标信号的欺骗干扰信号,对传统抗干扰雷达带来挑战。本文针对脉冲多普勒(Pulse Doppler,PD)雷达提出一种抗...抗干扰雷达长期以来是雷达领域的研究热点,数字射频存储器(Digital Radio Frequency Memory,DRFM)技术通过转发最大程度模拟真实目标信号的欺骗干扰信号,对传统抗干扰雷达带来挑战。本文针对脉冲多普勒(Pulse Doppler,PD)雷达提出一种抗DRFM转发式干扰方法,该方法通过对发射波形相位抖动调制,在保留雷达发射的脉冲相干性的同时,使雷达接收机在DRFM干扰设备没有对雷达发射信号完全接收转发的情况下,具有一定的抗欺骗干扰能力。仿真结果表明,通过提高相位调制幅度与调制单元数,可以有效提高真假目标辨别概率,同时,相位抖动使信号的峰值旁瓣电平(peak sidelobe level,PSL)提升和雷达的杂波抑制能力降低可控。展开更多
Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for...Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.展开更多
基金Supported by National High Technology Development Program of China (863-803-4-3)Scientific Research Fund of Sichuan Provincial Education Department (09ZA128)
文摘RF phase jitter is a very important parameter for a relativistic klystron amplifier. This parameter is closely linked with the physics processes in the klystron. RF phase jitter is theoretically studied together with Particle in Cell （PIC） simulations in the paper. The main factor is deduced and verified in the PIC simulation. RF phase jitter is significantly affected by the fluctuation of the beam voltage. The relation between the phase jitter and the voltage fluctuation is linear in certain ranges.
基金supported by the National Natural Science Foundation of China under Grant No.91336101 and No.61127901the West Light Foundation of the Chinese Academy of Sciences under Grant No.2013ZD02
文摘In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation frequencies, we calculate additional time jitters of these dividers by using the measured phase noise. The time jitters are various from -0.1 fs to 43 fs in a bandwidth from 1 Hz to 100 Hz in dependent of models and operation frequencies. The HMC series frequency dividers exhibit outstanding performance for high operation frequencies, and the time jitters can be sub-fs. The time jitters of SP8401, MC10EP139, and MC100LVEL34 are comparable or even below that of HMC series for low operation frequencies.
文摘抗干扰雷达长期以来是雷达领域的研究热点,数字射频存储器(Digital Radio Frequency Memory,DRFM)技术通过转发最大程度模拟真实目标信号的欺骗干扰信号,对传统抗干扰雷达带来挑战。本文针对脉冲多普勒(Pulse Doppler,PD)雷达提出一种抗DRFM转发式干扰方法,该方法通过对发射波形相位抖动调制,在保留雷达发射的脉冲相干性的同时,使雷达接收机在DRFM干扰设备没有对雷达发射信号完全接收转发的情况下,具有一定的抗欺骗干扰能力。仿真结果表明,通过提高相位调制幅度与调制单元数,可以有效提高真假目标辨别概率,同时,相位抖动使信号的峰值旁瓣电平(peak sidelobe level,PSL)提升和雷达的杂波抑制能力降低可控。
文摘Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.
