Phase-locked single-mode terahertz quantum cascade lasers array

We demonstrated a scheme of phase-locked terahertz quantum cascade lasers(THz QCLs)array,with a single-mode pulse power of 108 mW at 13 K.The device utilizes a Talbot cavity to achieve phase locking among five ridge lasers with first-order buried distributed feedback(DFB)grating,resulting in nearly five times amplification of the single-mode power.Due to the optimum length of Talbot cavity depends on wavelength,the combination of Talbot cavity with the DFB grating leads to better power amplification than the combination with multimode Fabry-Perot(F-P)cavities.The Talbot cavity facet reflects light back to the ridge array direction and achieves self-imaging in the array,enabling phase-locked operation of ridges.We set the spacing between adjacent elements to be 220μm,much larger than the free-space wavelength,ensuring the operation of the fundamental supermode throughout the laser's dynamic range and obtaining a high-brightness far-field distribution.This scheme provides a new approach for enhancing the single-mode power of THz QCLs.

An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

Joint MAP channel estimation and data detection for OFDM in presence of phase noise from free running and phase locked loop oscillator

This paper addresses a computationally compact and statistically optimal joint Maximum a Posteriori(MAP)algorithm for channel estimation and data detection in the presence of Phase Noise(PHN)in iterative Orthogonal Frequency Division Multiplexing(OFDM)receivers used for high speed and high spectral efficient wireless communication systems.The MAP cost function for joint estimation and detection is derived and optimized further with the proposed cyclic gradient descent optimization algorithm.The proposed joint estimation and detection algorithm relaxes the restriction of small PHN assumptions and utilizes the prior statistical knowledge of PHN spectral components to produce a statistically optimal solution.The frequency-domain estimation of Channel Transfer Function(CTF)in frequency selective fading makes the method simpler,compared with the estimation of Channel Impulse Response(CIR)in the time domain.Two different time-varying PHN models,produced by Free Running Oscillator(FRO)and Phase-Locked Loop(PLL)oscillator,are presented and compared for performance difference with proposed OFDM receiver.Simulation results for joint MAP channel estimation are compared with Cramer-Rao Lower Bound(CRLB),and the simulation results for joint MAP data detection are compared with“NO PHN"performance to demonstrate that the proposed joint MAP estimation and detection algorithm achieve near-optimum performance even under multipath channel fading.

A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop

In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

IDENTIFICATION OF PHASE ERROR BY MULTI-SAMPLING DIGITAL TANLOCKED LOOP(MS-DTL)

A multisampling technique was introduced to the phase error detector of Conventional Digital Tanlocked Loop(C DTL). In this new technique a number of samples ( M ) were taken at nonuniform intervals within one period of the input signal. The novel system is called Multisampling Digital Tanlocked loop(MS DTL). The simulated model on the computer shows that for M =4, the system has a faster locking speed and wider locking in range compared with C DTL.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

A Digital Phase Locked Loop Speed Control of Three Phase Induction Motor Drive: Performances Analysis

This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An ex-perimental verification is carried out on one kw scalar controlled IM system drives for a wide range of speeds and loads appliance. This presents a simple and high performance solution for industrial applications.

Novel Control Strategy for Multi-Level Active Power Filter without Phase-Locked-Loop

Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, there are some problems in the conventional method, such as the error of amplitude, the shift of phase angle and the non-determinacy of initial oriented angle. In this paper, two one-order low-pass filters are adopted instead of the pure integrator in the virtual line-flux-linkage observer, which can steady the phase and amplitude. Furthermore, an original scheme of harmonics detection under the rotating coordinate is advanced based on the simplified space vector pulse width modulation (SVPWM) strategy. Meanwhile, by using the new SVPWM algorithm, the voltage space vector diagram of the three-level inverter can be simplified and applied into that of two-level inverter, and this makes the control for Neutral Point potential easier.

Low phase noise millimeter wave monolithic integrated phase locked-loop

A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds.

THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

Multi-Order Intermittent Chaotic Synchronization of Closed Phase Locked Loop

For the model of a Closed Phase Locked Loop (CPLL) communication System consists of both the transmission and receiver ends. This model is considered to be in a multi-order intermittent chaotic state. The chaotic signals are then synchronized along side with our system. This chaotic synchronization will be demonstrated and furthermore, a modulation will be formed to examine the system if it will perfectly reconstruct or not. Finally we will demonstrate the synchronization conditions of the system.

A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop

Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

Error Correction Circuit for Single-Event Hardening of Delay Locked Loops

In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.

MICROPROCESSOR BASED PHASELOCKED LOOP SPEED CONTROL SYSTEM FOR AC MOTOR

In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is controlled by a 16-bit single chip microprocessor.A new type of frequency and phase detector is presented in detail,An adaptive method isadopted in speed controller.A three mode control scheme is used.These techniques are very use-ful to the improvement of the dynamic behavior of digital AC motor drive system.Experimental results show that the system is of good stability,high precision and good dynam-ic performance.

Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop

We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10?9 and a dynamic locking accuracy of about 5 × 10?8 are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on.

Propagation of phase-locked truncated Gaussian beam array in turbulent atmosphere

Truncation manipulation is a simple but effective way to improve the intensity distribution properties of the phase-locked Gaussian beam array at the receiving plane. In this paper, the analytical expression for the propagation of the phase-locked truncated Gaussian beam array in a turbulent atmosphere is obtained based on the extended Huygens--Fresnel principle. Power in the diffraction-limited bucket is introduced as the beam quality factor to evaluate the influence of different truncation parameters. The dependence of optimal truncation ratio on the number of beamlets, the intensity of turbulence, propagation distance and laser wavelength is calculated and discussed. It is revealed that the optimal truncation ratio is larger for the laser array that contains more lasers, and the optimal truncation ratio will shift to a larger value with an increase in propagation distance and decrease in intensity of atmosphere turbulence. The optimal truncation ratio is independent of laser wavelength.

A Digital Phase Lock Loop for an External Cavity Diode Laser

A digital optical phase lock loop(OPLL)is implemented to synchronize the frequency and phase between two external cavity diode lasers(ECDL),generating Raman pulses for atom interferometry.The setup involves all-digital phase detection and a programmable digital proportional-integral-derivative(PID)loop in locking.The lock generates a narrow beat-note linewidth below 1 Hz and low phase-noise of 0.03 rad2 between the master and slave ECDLs.The lock proves to be stable and robust,and all the locking parameters can be set and optimized on a computer interface with convenience,making the lock adaptable to various setups of laser systems.