A sapphire fibre thermal probe based on fast Fourier transform and phase-lock loop

A sapphire fibre thermal probe with Cr^3＋ ion-doped end is developed by using the laser heated pedestal growth method. The fluorescence thermal probe offers advantages of compact structure, high performance and ability to withstand high temperature in a detection range from room temperature to 450℃. Based on the fast Fourier transform （FFT）, the fluorescence lifetime is obtained from the tangent function of phase angle of the non-zeroth terms in the FFT result. This method has advantages such as quick calculation, high accuracy and immunity to the background noise. This FFT method is compared with other traditional fitting methods, indicating that the standard deviation of the FFT method is about half of that of the Prony method and about 1/6 of that of the log-fit method. And the FFT method is immune to the background noise involved in a signal. So, the FFT method is an excellent way of processing signals. In addition, a phase-lock amplifier can effectively suppress the noise.

Gigahertz frequency hopping in an optical phase-locked loop for Raman lasers

Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.

Digital-analog hybrid optical phase-lock loop for optical quadrature phase-shift keying

We analyze a feasible high-sensitivity homodyne coherent optical receiver for demodulating optical quadrature phase-shift keying(QPSK). A fourth-power phase-lock loop based on a digital look-up table is used. Considering the non-negligible loop delay, we optimize the loop natural frequency. Without error correction coding, a sensitivity of -37 dBm/-35 dBm is achieved, while the bit error rate is below 10-9 at 2.5 Gbaud/5 Gbaud rate.For the QPSK communication system, the bit rate is twice the baud rate. The loop natural frequency is 0.647 Mrad/s, and the minimized steady-state phase-error standard deviation is 3.83°.

11.6-GHz 0.18-μm monolithic CMOS phase-locked loop

A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Novel Control Strategy for Multi-Level Active Power Filter without Phase-Locked-Loop

Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, there are some problems in the conventional method, such as the error of amplitude, the shift of phase angle and the non-determinacy of initial oriented angle. In this paper, two one-order low-pass filters are adopted instead of the pure integrator in the virtual line-flux-linkage observer, which can steady the phase and amplitude. Furthermore, an original scheme of harmonics detection under the rotating coordinate is advanced based on the simplified space vector pulse width modulation (SVPWM) strategy. Meanwhile, by using the new SVPWM algorithm, the voltage space vector diagram of the three-level inverter can be simplified and applied into that of two-level inverter, and this makes the control for Neutral Point potential easier.

A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock's stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

CHAOS AND BIFURCATION OF PHASE-LOCKING LOOPS UNDER PERIODIC PERTURBATION

This paper discusses the chaos and bifurcation for equation x+cosxx+asinx =ebsint. By use of the Melnikov method the conditions to have the chaotic behavior and to have subharmonic oscillations are given.

量子Loop代数U_(q)(L(sl_(2)))的单权模

用构造的方法解决量子Loop代数U_(q)(L(sl_(2)))具有一个一维权空间的单权模的结构问题,得到了任意一个具有一维权空间的单权模必同构于U_(q)(L(sl_(2)))的四类单权模之一.此外,还构造了一类权空间维数为2的既非最高权也非最低权的量子Loop代数U_(q)(L(sl_(2)))的单权模.

Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop

We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10?9 and a dynamic locking accuracy of about 5 × 10?8 are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on.

A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop

In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.

Comparative Study of Low-Pass Filter and Phase-Locked Loop Type Speed Filters for Sensorless Control of AC Drives

High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.

Rapid and stable calcium-looping solar thermochemical energy storage via co-doping binary sulfate and Al–Mn–Fe oxides

Solar thermochemical energy storage based on calcium looping(CaL)process is a promising technology for next-generation concentrated solar power(CSP)systems.However,conventional calcium carbonate(CaCO_(3))pellets suffer from slow reaction kinetics,poor stability,and low solar absorptance.Here,we successfully realized high power density and highly stable solar thermochemical energy storage/release by synergistically accelerating energy storage/release via binary sulfate and promoting cycle stability,mechanical strength,and solar absorptance via Al–Mn–Fe oxides.The energy storage density of proposed CaCO_(3)pellets is still as high as 1455 kJ kg^(-1)with only a slight decay rate of 4.91%over 100 cycles,which is higher than that of state-of-the-art pellets in the literature,in stark contrast to 69.9%of pure CaCO_(3)pellets over 35 cycles.Compared with pure CaCO_(3),the energy storage power density or decomposition rate is improved by 120%due to lower activation energy and promotion of Ca^(2+)diffusion by binary sulfate.The energy release or carbonation rate rises by 10%because of high O^(2-)transport ability of molten binary sulfate.Benefiting from fast energy storage/release rate and high solar absorptance,thermochemical energy storage efficiency is enhanced by more than 50%under direct solar irradiation.This work paves the way for application of direct solar thermochemical energy storage techniques via achieving fast energy storage/release rate,high energy density,good cyclic stability,and high solar absorptance simultaneously.

THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.