Gigahertz frequency hopping in an optical phase-locked loop for Raman lasers

Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.

A Low-Power High-Frequency CMOS Peak Detector

A low-power,high-frequency CMOS peak detector is proposed. This detector can detect RF signal and base-band signal peaks. The circuit is designed using SMIC 0.35μm standard CMOS technology. Both theoretical calculations and post simulations show that the detection error is no more than 2% for various temperatures and processes when the input amplitude is larger than 400mV. The detection bandwidth is up to 10GHz, and its static current dissipation is less than 20μA.

Robust CMOS phase frequency detector for high speed and low jitter charge pump PLL

In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparisons are made. A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop （PLL） is designed. The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the LIP and DN signals to be logic-1 simultaneously. Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL. Furthermore, it has hardly any dead-zone phenomenon in phase characteristic. Simulations with ADS are performed based on a TSMC 0. 18-μm CMOS process with a 1.8-V supply voltage. According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency （≈ 1 GHz）, a wide phase-detection range [ ± 2π], a near zero dead-zone （ 〈 0. 1 ps）, high reliability, low phase jitter, low power consumption （ ≈100 μW） and small circuit complexity.

Design of 0.5V low-voltage phase and frequency detector for frequency synthesizer in wireless sensor networks

Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor networks（WSNs）.The PFD can compare the frequency and phase differences of input signals and deliver a signal voltage proportional to the difference.Low threshold transistors are used in the circuits since a power supply of 0.5V is adopted.A pulse latched structure is also used in the circuits in order to increase both the detection range of phase errors and the maximum operation frequency.In experiments,a phase error with a range from-358° to 358° is measured when the input signal frequency is 2MHz.The PFD has a faster acquisition speed compared with conventional digital PFDs.When the input signals are at a frequency of 2MHz with zero phase error,the circuits have a power consumption of 1.8[KG＊8]μW,and the maximum operation frequency is 1.25GHz.

Application of Different Frequency Domain Detectors in Radar Moving Target Detection

Moving target detection （MTD） technique is designed to filtering out the clutters. The basis of the MTD digital signal processor is a bank of Doppler filters designed using FFT algorithm. For high pulse repetition frequency （HPRF）, it leads to a long time calculations and great complexity in hardware implementation. Frequency domain detector is represented by Welch method Realized Doppler filters bank which will reduce the time calculation. The proposed method enhances the target detection capabilities by providing higher detection probabilities or lower false alarm rates. The performance of the two systems, the traditional MTD-I and Welch method are compared from the viewpoint of probability of detection （Pd）, probability of false alarm （Pfa）. Computer simulation results are presented to support the superiority of the proposed technique.

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications

A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.

On Optimal Frequencies of Acoustic in-situ Detector for Seafloor Hydrothermal Vents

The approach to determine working frequencies of acoustic in-situ detector for seafloor hydrothermal fluid is presented. Based on the research of deep-sea noise and the sound generated by mid-ocean ridge black smoker hydrothermal vents, and on the hydrothermal-vent animal hearing ranges, coupled with influences of suspended particles of hydrothermal on acoustic attenuation under different frequencies, the optimal frequency range for detection of acoustical signal near black smokers is determined. The optimal frequencies providing the maximum ratio of receiver signal to background noise are obtained. We have developed a laboratory experimental setup for the optimal frequencies selection. In particular, we evaluated time-of-flight performance with respect to the source signal parameters of center frequency and bandwidth. The experimental results confirm the effectiveness of our approach. Current results indicate that individual transducers operated in the range of 18 - 25 kHz are immune to most interfering sounds and suitable for our system.

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector

The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phase detector （FD＆PD） is described. A new automatic frequency band selection （FBS） without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.

A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application

A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.

Pump-induced carrier envelope offset frequency dynamics and stabilization of an Yb-doped fiber frequency comb

In this paper, we demonstrate a carrier envelope phase-stabilized Yb-doped fiber frequency comb seeding by a nonlinear-polarization-evolution（NPE） mode-locked laser at a repetition rate of 60 MHz with a pulse duration of 191 fs.The pump-induced carrier envelope offset frequency（ f0） nonlinear tuning is discussed and further explained by the spectrum shift of the laser pulse. Through the environmental noise suppression, the drift of the free-running f0 is reduced down to less than 3 MHz within an hour. By feedback control on the pump power with a self-made phase-lock loop（PLL）electronics the carrier envelope offset frequency is well phase-locked with a frequency jitter of 85 m Hz within an hour.

Comparative Study of Low-Pass Filter and Phase-Locked Loop Type Speed Filters for Sensorless Control of AC Drives

High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.

一种适用于亚采样锁相环的高鲁棒性辅助锁定电路

当前的研究表明,基于亚采样相位检测器(Sub-Sampling Phase Detectors,SSPD)的锁相环(Phase-Locked Loop,PLL)相较传统锁相环架构可以实现显著降低的带内相位噪声。然而,在片上系统(Systems on Chip,SOCs)应用中,PLL容易受到衬底或电源耦合的干扰,这很可能会导致PLL失去锁定,且可能无法恢复。针对此问题,提出一种将辅助锁频环(Frequency-Locked Loop,FLL)和数字锁定检测器(Digital Lock Detector,DLD)相结合的适用于亚采样锁相环(Sub-Sampling Phase-Locked Loop,SSPLL)的高鲁棒性辅助锁定电路。仿真结果表明:与传统SSPLL相比,所提出的电路极大提升了PLL对衬底或电源干扰的鲁棒性,同时保持了其低相位噪声的优点,这对于SSPLL在大规模生产和应用中的可靠性具有重要意义。

低抖动电荷泵锁相环设计及其Simulink建模仿真

随着集成电路工艺技术的进步,电路工作频率越来越高,对时钟信号的抖动和相噪也提出了更高的要求。针对锁相环电路参数多、结构复杂、瞬态仿真耗时长等问题,通过建立电荷泵锁相环系统环路数学模型,并运用MATLAB/Simulink对其进行负反馈系统建模,实现对电荷泵锁相环的快速动态仿真。在TSMC 65 nm CMOS工艺节点下,完成了锁相环的电路设计、版图绘制、物理验证并提取寄生参数及后仿真,得到一款典型值:输入频率为30 MHz,锁定频率1.5 GHz的低抖动电荷泵锁相环。后仿真结果表明该PLL电路性能指标良好,在典型值条件下,PLL的锁定时间为10μs,锁定时峰峰值抖动为2.68 ps,时钟信号占空比为45%。

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.

考虑历史地震烈度的楚雄州滑坡发育特征分析

楚雄州滑坡发育,影响因素复杂,处置困难。此研究以地质灾害调查数据为研究对象,选取岩层、构造、高程、坡度、坡向、历史地震烈度作为6个环境因子,采用频率比法揭示各环境因子优势区,并计算灾害易发性值,生成易发性等级图,指出楚雄州滑坡易发性高、中等级区域。基于地理探测器研究滑坡空间分布,量化各环境因子贡献度,讨论滑坡主导环境因子。最后,结合楚雄州降雨量分布探讨了滑坡诱发动力,并依据研究成果提出了针对性的防灾减灾建议。

贵州省土地利用变化频数分布及驱动因素

[目的]研究贵州省土地利用动态转移变化频数的空间格局及驱动因素,为该区土地调查工作与相关政策提供理论参考。[方法]基于2000—2020年贵州省土地利用数据,采用土地利用变化频数统计、核密度分析、空间自相关性等方法分析贵州省土地利用变化频率的时空分布特征,并借助地理探测器对其影响因素进行研究。[结果](1)贵州省2000—2020年土地利用变化频数中土地发生变化的面积仅为2%,但资金和人力的投入却相对较高,因此两者的投入关系极不协调。(2)贵州省2000—2020年土地利用变化频数中已变化的土地在空间分布上具有显著的空间异质性。(3)贵州省2000—2020年已变化土地核密度结果呈现“西高东低”的分布特征,土地变化1次的分布密度最大,土地变化3次的分布密度最小。(4)贵州省2000—2020年已变化土地和未变化土地皆呈显著空间集聚特征,已变化热点区域为赫章、大方等,未变化热点区域为威宁、从江等地区。(5)2000—2020年贵州省土地利用变化频数驱动因素的交互探测结果显示,坡度和坡向的交互作用对贵州省土地利用变化频数空间分异的解释力最强。[结论]贵州省土地利用变化频率分布具有显著的空间异质性,应建立贵州省土地利用变化频数监管机制,实现有效利用社会资源和减轻社会财政负担。

PEN衬底氧化镓基柔性紫外探测器的制备与性能研究(特邀)

针对传统硬性衬底无法弯折的问题,采用聚萘二甲酸乙二醇酯(PEN)衬底制备柔性紫外光电探测器。柔性衬底具有的抗曲折性,能够提升探测器的鲁棒性,并且能让其适用于各种复杂形态的应用场景,同时减少占用空间,有助于整个电路的集成化。实验使用磁控溅射镀膜工艺首先在PEN衬底上生长氧化镓薄膜,并在氧化镓薄膜上生长氧化铟锡电极,在室温下成功制备柔性氧化镓紫外光电探测器,器件响应波长处于小于280 nm的深紫外区。将器件弯折20000次后其暗电流无显著变化,光电流增大,保持了良好的紫外光探测性能,探测器上升时间和衰减时间分别为0.24 s/0.74 s和0.10 s/0.71 s,其电流-时间特性曲线呈现周期性稳定,表明即使经过多次弯折,柔性氧化镓紫外探测器仍然具有良好的光电探测性能。