Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping appro...Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.展开更多
This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthe...This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthesis. In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree (CST) algorithm optimizes the multi-input adder structure. The circuit has been verified through Matlab simulation, ASIC implementation, and FPGA experiment, which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.展开更多
The static comer frequency and dynamic comer frequency in stochastic synthesis of ground motion from fi- nite-fault modeling are introduced, and conceptual disadvantages of the two are discussed in this paper. Further...The static comer frequency and dynamic comer frequency in stochastic synthesis of ground motion from fi- nite-fault modeling are introduced, and conceptual disadvantages of the two are discussed in this paper. Furthermore, the non-uniform radiation of seismic wave on the fault plane, as well as the trend of the larger rupture area, the lower comer frequency, can be described by the source spectral model developed by the authors. A new dynamic comer frequency can be developed directly from the model. The dependence of ground motion on the size of subfault can be eliminated if this source spectral model is adopted in the synthesis. Finally, the approach presented is validated from the comparison between the synthesized and observed ground motions at six rock stations during the Northridge earthquake in 1994.展开更多
Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix(TM) of a scattering medium. We report a simple but powerful method, ...Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix(TM) of a scattering medium. We report a simple but powerful method, direct digital frequency synthesis(DDS) technology to modulate the phase front of the laser and measure the TM. By judiciously modulating the phase front of a He–Ne laser beam, we experimentally generate a high quality focus at any targeted location through a 2 mm thick 120 grit ground glass diffuser, which is commercially used in laser display and laser holographic display for improving brightness uniformity and reducing speckle. The signal to noise ratio(SNR) of the clear round focus is 50 and the size is about 44 μm. Our study will open up new avenues for enhancing light energy delivery to the optical engine in laser TV to lower the power consumption, phase compensation to reduce the speckle noise, and controlling the lasing threshold in random lasers.展开更多
The full-bridge converters usually use transformer leakage inductance and parallel resonant capacitors to achieve smooth current commutation and soft switching functions,which can easily cause problems such as energy ...The full-bridge converters usually use transformer leakage inductance and parallel resonant capacitors to achieve smooth current commutation and soft switching functions,which can easily cause problems such as energy leakage and significant duty cycle loss.This paper designs a novel full-bridge zero-current(FB-ZCS)converter with series resonant capacitors and proposes a frequency and phase-shift synthesis modulation(FPSSM)control strategy based on this topology.Compared with the traditional parallel resonant capacitor circuit,the passive components used are significantly reduced,the structure is simple,and there is only a slight energy loss.By controlling the charging time of the capacitor,it can be achieved without additional switches or auxiliary circuits.The automatic control of capacitor energy based on input current addresses the low efficiency of the traditional control strategies.This paper introduces its principle in detail and verifies it through simulation.Finally,an experimental prototype was built further to demonstrate the feasibility of the theory through experiments.The module can be applied to a photovoltaic DC collection system using input parallel output series(IPOS)cascade to provide a new topology for large-scale,long-distance DC transmission.展开更多
Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calib...Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calibration tactics has been carried out to rectify this defect.It is optimized for implementation in FPGA.Mathematical illustrations of the calibration method,hardware and software design and implementation are presented.A signal source circuit using frequency synthesis technique is designed as calibration standard.Data acquisition system using JAVA web technology and Ethernet is introduced.Integrated FPGA implementation code architecture is presented,and experimental test results show that the method implemented in FPGA is feasible.Compared to other methods,our approach can rectify the nonlinearity and asymmetry simultaneously.The whole solution is integrated into the DBPM processor and can be executed online.展开更多
A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant ac...A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator(VCO)are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature(IQ)signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency(RF) complementary metal oxide semiconductor transistor (CMOS)technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.展开更多
The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL's loop dynamics are analyzed in depth and theoreti...The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL's loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL's output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor (CMOS) technology.展开更多
In the digital synthesis of wideband periodic signals using an Arbitrary Waveform Gen-erator(AWG),the frequency resolution and spectral complexity of the synthesized signals are com-monly limited by the memory capacit...In the digital synthesis of wideband periodic signals using an Arbitrary Waveform Gen-erator(AWG),the frequency resolution and spectral complexity of the synthesized signals are com-monly limited by the memory capacity and clock frequency of the AWG.This paper proposes a novel sequential addressing scheme and then presents several sequences to improve the frequency resolution of the synthesized periodic signals without changing their spectral envelopes and basic time-domain characteristics under the condition of a fixed memory capacity and a fixed clock fre-quency.The main idea of the scheme is using the address generator in an AWG to program and produce addresses to read fixed waveform data in variable order,and thus to generate waveforms of various periods and profiles.The scheme is applied in simulating signal scenarios for military com-munication countermeasure experiments,and achieves high performance.展开更多
Based on the analysis of the spurious introduced by phase accumulation truncation which was made by Nicholas, a new simplified algorithm for spurious spectrum in the presence of phase truncation is presented by using ...Based on the analysis of the spurious introduced by phase accumulation truncation which was made by Nicholas, a new simplified algorithm for spurious spectrum in the presence of phase truncation is presented by using the mapping mathematics and number theoretic method, it is possible to precisely analyze the spurious location and the spurious amplitude introduced by phase truncation in practical applications by computer.展开更多
A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel...A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.展开更多
This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep ...This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.展开更多
Monodispersive ZnO nanoparticles each with a hexagonal wurtzite structure are facilely prepared by the hightemperature organic phase method.The UV-visible absorption peak of ZnO nanoparticles presents an obvious blue-...Monodispersive ZnO nanoparticles each with a hexagonal wurtzite structure are facilely prepared by the hightemperature organic phase method.The UV-visible absorption peak of ZnO nanoparticles presents an obvious blue-shift from 385 nm of bulk ZnO to 369 nm.Both the real part and the image part of the complex permittivity of ZnO nanoparticles from 0.1 GHz to 10 GHz linearly decrease without obvious resonance peak appearing.The real parts of intrinsic permittivity of ZnO nanoparticles are about 5.7 and 5.0 at 0.1 GHz and 10 GHz respectively,and show an obvious size-dependent behavior.The dielectric loss angle tangent(tan 5) of ZnO nanoparticles with a different weight ratio shows a different decreasing law with the increase of frequency.展开更多
The title molecule, 3-(4-(dimethylamino)benzylidene)-l,5-dioxaspiro[5.5] unde- cane-2,4-dione (I), was synthesized and characterized by elemental analysis, IR, UV-vis spectra and X-ray diffraction analysis. The ...The title molecule, 3-(4-(dimethylamino)benzylidene)-l,5-dioxaspiro[5.5] unde- cane-2,4-dione (I), was synthesized and characterized by elemental analysis, IR, UV-vis spectra and X-ray diffraction analysis. The compound belongs to the triclinic system, space group Pi with a = 6.3640(6), b = 7.7404(8), c = 16.2890(18) A, α = 86.860(2), β = 85.837(2), γ = 79.6720(10)°, V = 786.60(14) A3, D, = 1.331 g/cm3, and F(000) = 336. Geometrical structure of the title compound was optimized by density functional theory (DFT) using B3LYP method with 6-31G** as the basis set. The vibrational frequencies were calculated by the DFT method and the results are consistent with the observed frequencies. The electronic absorption spectra were studied with the time- dependent density functional theory (TD-DFT), showing the calculation results in good agreement with the corresponding experimental data.展开更多
In this paper, we demonstrate a carrier envelope phase-stabilized Yb-doped fiber frequency comb seeding by a nonlinear-polarization-evolution(NPE) mode-locked laser at a repetition rate of 60 MHz with a pulse durati...In this paper, we demonstrate a carrier envelope phase-stabilized Yb-doped fiber frequency comb seeding by a nonlinear-polarization-evolution(NPE) mode-locked laser at a repetition rate of 60 MHz with a pulse duration of 191 fs.The pump-induced carrier envelope offset frequency( f0) nonlinear tuning is discussed and further explained by the spectrum shift of the laser pulse. Through the environmental noise suppression, the drift of the free-running f0 is reduced down to less than 3 MHz within an hour. By feedback control on the pump power with a self-made phase-lock loop(PLL)electronics the carrier envelope offset frequency is well phase-locked with a frequency jitter of 85 m Hz within an hour.展开更多
In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at h...In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.展开更多
High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase...High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.展开更多
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2021YFA0718300 and 2021YFA1400900)the National Natural Science Foundation of China(Grant Nos.11920101004,11934002,and 92365208)+1 种基金Science and Technology Major Project of Shanxi(Grant No.202101030201022)Space Application System of China Manned Space Program.
文摘Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.
文摘This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthesis. In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree (CST) algorithm optimizes the multi-input adder structure. The circuit has been verified through Matlab simulation, ASIC implementation, and FPGA experiment, which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.
基金supported by National Natural Science Foundation of China under grant No. 50778058 and 90715038National Key Technology Research and Development Program under grant No. 2006BAC13B02
文摘The static comer frequency and dynamic comer frequency in stochastic synthesis of ground motion from fi- nite-fault modeling are introduced, and conceptual disadvantages of the two are discussed in this paper. Furthermore, the non-uniform radiation of seismic wave on the fault plane, as well as the trend of the larger rupture area, the lower comer frequency, can be described by the source spectral model developed by the authors. A new dynamic comer frequency can be developed directly from the model. The dependence of ground motion on the size of subfault can be eliminated if this source spectral model is adopted in the synthesis. Finally, the approach presented is validated from the comparison between the synthesized and observed ground motions at six rock stations during the Northridge earthquake in 1994.
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2016YFB0401902 and 2016YFB0402001)Key-Area Research and Development Program of Guang Dong Province,China(Grant No.2019B010926001)。
文摘Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix(TM) of a scattering medium. We report a simple but powerful method, direct digital frequency synthesis(DDS) technology to modulate the phase front of the laser and measure the TM. By judiciously modulating the phase front of a He–Ne laser beam, we experimentally generate a high quality focus at any targeted location through a 2 mm thick 120 grit ground glass diffuser, which is commercially used in laser display and laser holographic display for improving brightness uniformity and reducing speckle. The signal to noise ratio(SNR) of the clear round focus is 50 and the size is about 44 μm. Our study will open up new avenues for enhancing light energy delivery to the optical engine in laser TV to lower the power consumption, phase compensation to reduce the speckle noise, and controlling the lasing threshold in random lasers.
基金This work was supported by the Key R&D Program of Tianjin(No.20YFYSGX00060).
文摘The full-bridge converters usually use transformer leakage inductance and parallel resonant capacitors to achieve smooth current commutation and soft switching functions,which can easily cause problems such as energy leakage and significant duty cycle loss.This paper designs a novel full-bridge zero-current(FB-ZCS)converter with series resonant capacitors and proposes a frequency and phase-shift synthesis modulation(FPSSM)control strategy based on this topology.Compared with the traditional parallel resonant capacitor circuit,the passive components used are significantly reduced,the structure is simple,and there is only a slight energy loss.By controlling the charging time of the capacitor,it can be achieved without additional switches or auxiliary circuits.The automatic control of capacitor energy based on input current addresses the low efficiency of the traditional control strategies.This paper introduces its principle in detail and verifies it through simulation.Finally,an experimental prototype was built further to demonstrate the feasibility of the theory through experiments.The module can be applied to a photovoltaic DC collection system using input parallel output series(IPOS)cascade to provide a new topology for large-scale,long-distance DC transmission.
基金Supported by the National Natural Science Foundation of China(No.11075198)
文摘Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calibration tactics has been carried out to rectify this defect.It is optimized for implementation in FPGA.Mathematical illustrations of the calibration method,hardware and software design and implementation are presented.A signal source circuit using frequency synthesis technique is designed as calibration standard.Data acquisition system using JAVA web technology and Ethernet is introduced.Integrated FPGA implementation code architecture is presented,and experimental test results show that the method implemented in FPGA is feasible.Compared to other methods,our approach can rectify the nonlinearity and asymmetry simultaneously.The whole solution is integrated into the DBPM processor and can be executed online.
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z2A7)the Scienceand Technology Program of Zhejiang Province (No.2008C16017)
文摘A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator(VCO)are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature(IQ)signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency(RF) complementary metal oxide semiconductor transistor (CMOS)technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.
基金supported by the National Natural Science Foundation of China under Grant No. 61006027the New Century Excellent Talents Program of China under Grant No. NCET-10-0297
文摘The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL's loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL's output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor (CMOS) technology.
基金the National Grand Fundamental Research 973 Program of China (No.2004CB318109)the National High-Technology Research and Development Plan of China (No.2006AA01Z452)
文摘In the digital synthesis of wideband periodic signals using an Arbitrary Waveform Gen-erator(AWG),the frequency resolution and spectral complexity of the synthesized signals are com-monly limited by the memory capacity and clock frequency of the AWG.This paper proposes a novel sequential addressing scheme and then presents several sequences to improve the frequency resolution of the synthesized periodic signals without changing their spectral envelopes and basic time-domain characteristics under the condition of a fixed memory capacity and a fixed clock fre-quency.The main idea of the scheme is using the address generator in an AWG to program and produce addresses to read fixed waveform data in variable order,and thus to generate waveforms of various periods and profiles.The scheme is applied in simulating signal scenarios for military com-munication countermeasure experiments,and achieves high performance.
文摘Based on the analysis of the spurious introduced by phase accumulation truncation which was made by Nicholas, a new simplified algorithm for spurious spectrum in the presence of phase truncation is presented by using the mapping mathematics and number theoretic method, it is possible to precisely analyze the spurious location and the spurious amplitude introduced by phase truncation in practical applications by computer.
基金Funded by the Communication System Project of Jiangsu Provincial Education Committee under grant No.JHB04010
文摘A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.
文摘This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.
基金supported by the National Natural Science Foundation of China(Grant Nos.11274370 and 51471185)the National Basic Research Program of China(Grant Nos.2012CB933102 and 2011CB921801)
文摘Monodispersive ZnO nanoparticles each with a hexagonal wurtzite structure are facilely prepared by the hightemperature organic phase method.The UV-visible absorption peak of ZnO nanoparticles presents an obvious blue-shift from 385 nm of bulk ZnO to 369 nm.Both the real part and the image part of the complex permittivity of ZnO nanoparticles from 0.1 GHz to 10 GHz linearly decrease without obvious resonance peak appearing.The real parts of intrinsic permittivity of ZnO nanoparticles are about 5.7 and 5.0 at 0.1 GHz and 10 GHz respectively,and show an obvious size-dependent behavior.The dielectric loss angle tangent(tan 5) of ZnO nanoparticles with a different weight ratio shows a different decreasing law with the increase of frequency.
基金Project supported by the Natural Science Foundation of Shandong Province(Nos.ZR2010CL011 and ZR2010BM033)
文摘The title molecule, 3-(4-(dimethylamino)benzylidene)-l,5-dioxaspiro[5.5] unde- cane-2,4-dione (I), was synthesized and characterized by elemental analysis, IR, UV-vis spectra and X-ray diffraction analysis. The compound belongs to the triclinic system, space group Pi with a = 6.3640(6), b = 7.7404(8), c = 16.2890(18) A, α = 86.860(2), β = 85.837(2), γ = 79.6720(10)°, V = 786.60(14) A3, D, = 1.331 g/cm3, and F(000) = 336. Geometrical structure of the title compound was optimized by density functional theory (DFT) using B3LYP method with 6-31G** as the basis set. The vibrational frequencies were calculated by the DFT method and the results are consistent with the observed frequencies. The electronic absorption spectra were studied with the time- dependent density functional theory (TD-DFT), showing the calculation results in good agreement with the corresponding experimental data.
基金Project supported by the National Natural Science Foundation of China(Grant No.11274115)the National Key Project for Basic Research,China(Grant No.2011CB808105)the National Key Scientific Instrument Project,China(Grant No.2012YQ150092)
文摘In this paper, we demonstrate a carrier envelope phase-stabilized Yb-doped fiber frequency comb seeding by a nonlinear-polarization-evolution(NPE) mode-locked laser at a repetition rate of 60 MHz with a pulse duration of 191 fs.The pump-induced carrier envelope offset frequency( f0) nonlinear tuning is discussed and further explained by the spectrum shift of the laser pulse. Through the environmental noise suppression, the drift of the free-running f0 is reduced down to less than 3 MHz within an hour. By feedback control on the pump power with a self-made phase-lock loop(PLL)electronics the carrier envelope offset frequency is well phase-locked with a frequency jitter of 85 m Hz within an hour.
基金the Natural Science Foundation of Hei- longjiang Province, China (F2004-17).
文摘In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.
基金This work was supported in part by Lodam A/S and in part by the PSO-ELFORSK Program。
文摘High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.